When should use Internal, crystal and PLL in PIC 1846k22 MCU CCS C Compilers

[dattlara76]

Hi,

As by default PLL is enable in the 18F46k22. If so with the code below ,

#
include <18F46K22.h>
#fuses  NOMCLR,NOLVP,NOBROWNOUT,PUT,NOXINST
#use delay(internal = 64MHz) //ORI 8//BY DEFAULT PLL IS ENABLE SO 20 crystal is used the 20X4 =80MHZ

will be the FOSC = 64Mhz and then Instruction Clock =64/4=16MIPS ? Is this correct or it will be mutiplied by PLL, I am confused??

If //#use delay (clock=20MHZ, crystal) and if the fuse is above then what should be mulplier PLL, will it be 4x20=80MHZ FOSC.??

If we are in requirement of less than or equal to 64mhz of FOSC then why should we use crystal to get 64MHZ with 16MHZ crystal with PLL. ???

Please any one let me know the actual cause of all my 3 questions.
Thank you...

 

[FvM]

The idea that #use delay sets the oscillator configuration completely doesn't work in all cases (or at least not in all CCS C versions and for all processors. It's however required to inform the compiler about the actual clock speed for various timings, e.g. timer and baud rate settings or software delays.

In case of 18F46K22 you can e.g. write

#use delay (xtal=16Mhz, clock=64Mhz)

to setup a 16 MHz crystal with x4 PLL

In contrast

#use delay (int=16Mhz, clock=64Mhz)

misses to enable the PLL

I suggest

#use delay(clock=64Mhz)
#fuses INTRC_IO, PLLEN, NOIESO, NOFCMEN

to setup all oscillator related configuration bits explicitly.

In any case you need to check if the intended clock configuration is feasible for the actual supply voltage and temperature range.