It seems to me, that you didn't understand yet what the bottlenecks of a logic analyzer are. For the project, it's pretty necessary to understand it!
Let me mention a few keywords first:
1. Clocking
2. Triggering
3. Data storage
1. Most logic analyzers have an option to use an external clock from the application alternatively to an internal clock. It's necessary if you want to acquire a signal, that is e. g. faster than 1/10 of your logic analyzer maximum sampling rate. It may be omitted, if the LA is intended for asynchronous or slow applications only,
2. A suitable triggering logic is necessary in most cases to detect events from the bitstreams presented to the LA and start or stop acquisition. It has to operate in real-time at sampling speed usually.
3. The most important point is the data path. You have to establish a data storage of sufficient capacity that can write data continously at the intended sampling rate. It's effectively impossible to store a data stream of 100 MByte/s at a PC that runs a standard OS, even if the interface would be fast enough (Gigabit Ethernet or PCI Express have a troughput in this region). And 100 MByte/s isn't enough for a fast LA. Thus a dedicated local data storage is needed.
As a result, a FPGA, probably supplemented by fast external memory, is a appropriate design platform for a low cost LA. Cause data transmission to the controlling PC is freed from real-time requirements, it may use any avalable channel, even RS232. But a faster interface (USB, Ethernet) is preferable, although it needs additional hardware and supporting logic.
An USB microprocessor with a fast data interface, e. g. a Cypress FX2 could act as control and data channel and also perform the FPGA configuration.