joe2moon
Full Member level 5
I have a question about how will you handle the following case:
When using FPGA verification to verify the ASIC design,
if the really ASIC uses asynchronous SRAM(s) inside the chip,
and the FPGA device only has synchronous SRAM(s), then
the HDL code should be different.
However, in this case, the design verified on FPGA and the design
really tapeout would be different, too.
Any way to skip this condition ?
Thanks.
When using FPGA verification to verify the ASIC design,
if the really ASIC uses asynchronous SRAM(s) inside the chip,
and the FPGA device only has synchronous SRAM(s), then
the HDL code should be different.
However, in this case, the design verified on FPGA and the design
really tapeout would be different, too.
Any way to skip this condition ?
Thanks.
