[SOLVED] When do I use real clock in synthesis?

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Hi.

As I know, the clock skew is that clock signal arrives at different flip-flop at different time.
Also When I synthesis, I use ideal clock not real clock to synthesis.
The when do I use real clock to synthesis?
Is this same thing clock skew and clock uncertainty?.
How can I avoid clock skew problem and clock uncertainty?

- - - Updated - - -

Also, what is the useful skew?
 

In general, if the design passes synthesis at your expected frequency, always (and I repeat, always) latch at rising edge, read at falling edge (or vice-versa). I can't tell you how many times I had a failed design without the slightest explanation as it passed DRC and Testbench, but failed the real environment...

Hope this helps
 

well this problem is solved by multitude of tools during timing , physically aware placement and sign off. It is not advisable to use real clock in synthesis as you don't have parasitic which is more important in the smaller technologies. Once you have done the placement, the CTS will take care of the timing and try to balance the clock across various flops which takes care of clock skew. Clock uncertainty is also analyzed using the on chip variation models for the clock cells.

Useful skew is the timing that can used to delay the clock from one flop to another flop depending upon the logic between them. This will be covered in detail in any ASIC design book.
 

Hi,

As i could see, you missed the idea of the ASIC flow.

There are series of steps followed one after another, to send a chip for fabrication at the earliest time.

Once, RTL is ready, it is taken for synthesis. Synthesizing means to only convert the CODE to gate level netlist.
During synthesis, you do not have any idea of the real clock. Because, real clock is not build during the synthesis stage. Real Clock is build during the physical design stage.

So during the synthesis stage, we add extra uncertainty which would account for Skews.
 

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