When designing an IC layout, does the width of the metal need to ensure peak current?

dick_freebird said:

This also has underlying process construction
details to consider (must derive from physics of
failure).

For example an all-aluminum (planes and vias)
system will let electromigration proceed through
layer, via, layer and the material drift somewhat
maintains the distribution (choke-points where
J is most elevated, aside - uniform J is constant /
uniform-ish material drift).

But tungsten plugs are hard migration barriers so
what you see there is, material accumulates at the
"upstream" side and "wanders away" from the
downstream of current flow. You can see worse
EM outcomes from equal interconnect-plane
material properties, using W plug vias.

Not to mention that the plugs are nasty little heaters
that locally raise interconnect temp (the prime
accelerant) and can torpedo your current capacity
(rules, not facts) if analysis fails to comprehend /
account for / put to lifetime model at stress-temp
and stress-self-heating.

Of course by the time a designer sees the rules, all
of this has long since been "blessed" and any effort
to check work will meet resistance (heh). Believe me,
I have gone down that road (finding and fixing bad
electromigration test conduct and analysis and the
clowns who made it so) more than once.

Click to expand...

dick_freebird said:

This also has underlying process construction
details to consider (must derive from physics of
failure).

For example an all-aluminum (planes and vias)
system will let electromigration proceed through
layer, via, layer and the material drift somewhat
maintains the distribution (choke-points where
J is most elevated, aside - uniform J is constant /
uniform-ish material drift).

But tungsten plugs are hard migration barriers so
what you see there is, material accumulates at the
"upstream" side and "wanders away" from the
downstream of current flow. You can see worse
EM outcomes from equal interconnect-plane
material properties, using W plug vias.

Not to mention that the plugs are nasty little heaters
that locally raise interconnect temp (the prime
accelerant) and can torpedo your current capacity
(rules, not facts) if analysis fails to comprehend /
account for / put to lifetime model at stress-temp
and stress-self-heating.

Of course by the time a designer sees the rules, all
of this has long since been "blessed" and any effort
to check work will meet resistance (heh). Believe me,
I have gone down that road (finding and fixing bad
electromigration test conduct and analysis and the
clowns who made it so) more than once.

Click to expand...