Gated clocks are used under some constraints .. usually circuits used for that are technology dependant and can be infered during synthesis if your RTL was originally coded in a specific style/way in order to do that ..
The question is if You have to use it or not. Generally clock gating is not always simple and may couze problems like one You described. But in moder circuits power comsumption is very important not only in battery using things but in microprocesors also. So better get used to clock gating and other poser saving techniques like changes Vt or sleep modes.
Gated clock is useful not only for reducing power consumption.
The digital blocks with gated clock generate much less switching noise.
If your application used high resolution ADC you should care about that also.