wheater signal or varuable while assigning inputs

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harian

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hi. i have question regarding using variable or signal--
i have given a list of std vectors , i want these as input to my ports say to Op_1 and op_2. i have alittle bit doubt wheather to use signal or variable..

using variable

Code: 
type bit_vector_0 is array(1 to 10) of std_logic_vector(3 downto 0);
type bit_vector_1 is array(1 to 10) of std_logic_vector(3 downto 0);
process
variable b1 :bit_vector_0:=(others=>"0000");
variable b1 :bit_vector_1:=(others=>"0000");

begin 
for i in 0 to 10 loop
op_:=b0;
op_1:=b1;
wait for 1 ns;
end loop;
end process

using signals
Code: 
type bit_vector_0 is array(1 to 10) of std_logic_vector(3 downto 0);
type bit_vector_1 is array(1 to 10) of std_logic_vector(3 downto 0);

signal b1 :bit_vector_0:=(others=>"0000");
signal b1 :bit_vector_1:=(others=>"0000");
wait for 1 ns;
process
begin 
for in 1 to 10 loop
op_:=b0;
op_1:=b1;
wait for 1 ns
end loop;
end process
what is the difference between these two codes,,
 

The difference between the 2 will be that in case of signals,b1 can be used out the process block while in case of variables b1 is restricted to usage within that process block.
Another difference is that variables get assigned immediately while signals don't.
 

This is a poorly written question with a badly written example of what you are asking. The code you wrote doesn't assign anything to the variable b0 & b1 or to the signals b0 & b1. You are doing a variable assignment to your port inputs (whatever that is supposed to mean...is this the entity ports or the ports on a component?) op_ and op_1, which might not even be legal VHDL depending on what input port you are talking about. Out of context code fragments are usually a poor way to communicate your intentions and they don't allow you to verify if they actually compile (I'm sure you didn't even try to do that).

The real answer to this question of using variables or signals is...I've never found a case where I had to use a variable in place of a signal to make code that "works". The only times I've ever used a variable was when I was trying to make the code more understandable. One place variables make sense is when it's used as the array in the model of a memory, variables will simulate faster than a signal array, since variables don't need to be scheduled.
 


I would agree with this - for RTL code that is indended for synthesis.
The OPs code is clearly for a testbench, where variables can be very useful and important.

harian: You example is very poor. As has already been pointed out, variables can only live inside processes/functions/procedures (unless they are shared variables) and signals can only be declared inside packages/architectures. So from your examle, as B0 and B1 are never assigned, there is no difference in the two codes.

I highly suggest you find the variables vs signals section of your tutorial.
 



u r right, it is a bad formulated question. I have not simulated the code.I am just trying to find out what is the difference between signal and variable in case of assigning value to component Inputs from a array.
i need to write a test bench to assign array to component Ports. while i am using for loop, i m littel bit confused wheather to use signal or variable. as in the code example.. The question was not wheather it is bad or good ,,wheather i have simulated,, i just wanted to know ,,wheather to use signal for loop or variable ,,
as i was told, variable are assigned in process sequencly but signals parallel. i thought signals would be more senseful because both inputs op_1,2 are assignes at same time the value i.. and not one after another
 

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