What's then matter with my testbench code?

[zpmanr]

process(data_en2_to_assemble)
begin
if rising_edge(data_en2_to_assemble) then
wait for 5*period;
DataBuff_empty_flag(3) <= '0';
wait for 100*period;
DataBuff_empty_flag(3) <= '1';
end if;
end process;

When I use Modelsim to sim,there is always a error.
I want to know how to resolve this problem or how to optimize this section code.
Thanks.

 

[nand_gates]

Its simple !!!
If you are using wait statement inside process then that process should not
have sensitivity list modify ur code as follows it will work

process
    begin
       wait until data_en2_to_assemble;
           wait for 5*period;
           DataBuff_empty_flag(3) <= '0';
           wait for 100*period;
           DataBuff_empty_flag(3) <= '1';
end process;

 

[neocool]

I have another question here on different topic but using the same code example.
Is it more efficient to use multiplication here if 'period' is just an integer constant (i.e. 5*period) or to sum period five times?
I know that for signals, multiplication takes quite a lot of space on fpga, but not sure how it is in this case.
Thanks

 

[eziggurat]

Isn't this is a testbench? You can't synthesise wait statements. If want to reduce the logic for multiplication, you can use shift and add. Look at distributed arithmetic.

 

[neocool]

Isn't this is a testbench? You can't synthesise wait statements. If want to reduce the logic for multiplication, you can use shift and add. Look at distributed arithmetic.

so, are you saying that using regular '*' statement from std_logic_arith library on 16-bit vectors for example will take a LOT of space comparted to distributed arithmetic?
where can I find a good algorythm for distributed arithmetic?

Best Regards

 

[eziggurat]

Note, std_logic_arith library is not a standardised library for VHDL. Check this thread in google newsgroup for example, https://groups.google.co.uk/groups?...=10l641nl9jebu1e%40corp.supernews.com&rnum=29

You can always look at www.andraka.com on distributed arithmetic.

 

[neocool]

Thanks for the great link!

Are there any other good boards on VHDL and digital design?

As of regards to multiplication, I was working on filter that stores results in registers.. so regular synthesis takes a lot of space.. I thought it was due to multiplication, but I guess mainly it's because of that. I will try to use block ram to reduce the space.

How much space does regular '*' multiplication take (i.e. using numeric_std) as compared to some other fast available multiplication algorythms. Also, is there a free code for them? Andraka.com seems to have only description.

Thanks

 

[eziggurat]

Have you tried tech-www.informatik.uni-hamburg.de/vhdl/ or www.stefanvhdl.com/.

Try typing into google.

For the multiplication, I don't actually know the usage but that usually depends on the synthesis tool/FPGA and also the size of the inputs you are using.

I am sure you can find that out by typing into google again. There is also a good book in the mcufileman on DSP using FPGA but you would have to search the Edaboard for it.