guow06
Junior Member level 3
I'm designing a comparator for my 10-bit SAR ADC. Just wondering what's the typical value of the comparator's input offset with careful layout. For 10-bit ADC, do I need to do offset cancellation?
I have done a simple dynamic comparator and the post-layout simulation result shows about 1mV offset. Will it be better if I add a preamplify-stage? (The whole ADC post-layout simulation shows a good result without offset cancellation though)
I have done a simple dynamic comparator and the post-layout simulation result shows about 1mV offset. Will it be better if I add a preamplify-stage? (The whole ADC post-layout simulation shows a good result without offset cancellation though)