the end result will be that a and c are wires connected to power, b is a wire connected to ground. This is the same as though you had simply written a := '1'; b := '0'; c := '1'
Hey "pongetti" thanks for your explanation. I'm unclear with one more fact. I've understood that only signals are wires connected to Vcc for '1' and Gnd for '0',whereas variables are for local storage. So I thought it may infer flipflops for storing '1's and '0'. Ok consider this eg.,
----------------
PROCESS(clk) IS
VARIABLE data_stack : STD_LOGIC_VECTOR(7 DOWNTO 0);
begin
data_stack := "10011010";
end process;
-----------------
Here,as per what you have said,does this variable "data_stack" be declared as series of 8-set wires(bus) connected to Vcc and Gnd as per it's assignment?...Ok if it's the actual case, then what happens when I drive this with some other source,for eg
-----------------------------------
PROCESS(clk,incr_val) IS
VARIABLE data_stack : STD_LOGIC_VECTOR(7 DOWNTO 0);
begin
IF RISING_EDGE(clk) THEN
data_stack := data_stack + incr_val;
end if;
end process;
----------------------------------
So in this approach how will the variable be treated?....Local storage or a bus type declaration?...Whether the synthesizer will infer flipflops for storage or just ignore?....Please illustrate....Thanks a thousand for your helping minds.