What's the role of this NMOS?

[wjxcom]

Hi all, I am designing a circuit shown in the picture below

In this circuit, there have a NMOS whose name is NM0. I don't understand what's the role of it.
In fact, this circuit is a power supply and produces a 1V voltage to a DLL (delay phase lock).
How can I understand the nmos NM0? what's the role of it?
Help me please, thanx!!

And, what's the role of the capacitance？

 

[northumber82]

The structure is much similar to a class A configuration amplifier, with a differential input stage and the output stage as a cascade of nMOS or NPN transistors.

PM are the mirror that deal with equalizing the current between the two arms of the differential, the capacitance is probably a cuf-off capacitor for high-frequencies.

 

[t4_v]

northumber82 put it correct. It's 2-stages class-A opamp. The 1st stage is NMOS differential pair loaded by PMOS current mirror. The 2nd stage is a buffer. It provides high currents to the load. This action is done by NM transistor. NM0 is just a current source. You need to bias NM (from the 2nd stage) and it is done by the current of NM0. Take a look here: https://en.wikipedia.org/wiki/Buffer_amplifier .

You may find a lot of useful information about class A architecture in books as Razavi or Baker. You may also take a look here: https://payhip.com/b/5Srt at page 50 (chapter 3.1.1) in the preview.

 

[FvM]

NM0 is just a current source.

Could be expected, but the schematic is wrong in this case by driving NM0 gate with Vip rather than Vb.

 

[t4_v]

Sure, it would be expected that NM0 would have the gate bias equal to VB, but in the case that VIP = 1V DC only (no AC signal), NM0 may be biased by 1V and sized properly.

 

[erikl]

... but in the case that VIP = 1V DC only (no AC signal), NM0 may be biased by 1V and sized properly.

And where, in this case, would be the OTA's input?

@wjxcom: Cc operates as Miller compensation capacitor, its value being multiplied by the right PM's (low) gain - for low frequencies; for high frequencies (PM's gain<1) it operates as feedforward capacitor.

BTW: The right diff-amp's NM and the upper source follower output NM constitute a built-in negative feedback loop.

 

[t4_v]

And where, in this case, would be the OTA's input?

In fact, this circuit is a power supply and produces a 1V voltage to a DLL (delay phase lock).

VIP is the input. It is equal to 1V DC voltage.

 

[erikl]

VIP is the input. It is equal to 1V DC voltage.

You're right. I forgot that it's a pure DC circuit.

 

[wjxcom]

Hi all: I perform the ac simulation for the circuit. the bode curve is the picture above. From the curve, we can know that the PhaseMargin is bad. But if I connect the gate of NM0 to VB other than VIP, the bode curve is very good!
If the gate of NM0 is connected to VB, the VIP is the positive port of the opa, but now the gate of NM0 is connected to VIP, so VIP becomes a negative port of the opa. It's so strange!

- - - Updated - - -

Hi erikl, what's the meaning of "a pure DC circuit"? How can I understand this sentence?

 

[t4_v]

Hi,

You should really take a look into proper materials, e.g. ones that I mentioned previously, to understand the architecture you're designing.

Usually, NM0 should be connected to VB not VIP. Your circuit is a pure DC circuit, because you explained that the VIP = 1 V DC. No AC signal.

 

[erikl]

Hi erikl, what's the meaning of "a pure DC circuit"? How can I understand this sentence?

It's already correctly explained, I think:

Your circuit is a pure DC circuit, because you explained that the VIP = 1 V DC. No AC signal.

 

[erikl]

But if I connect the gate of NM0 to VB other than VIP, the bode curve is very good!

It's the correct connection, I think, if you are content with the function.

If the gate of NM0 is connected to VB, the VIP is the positive port of the opa, ...

Because there are 2 signal inversions from VIP to VO.

... but now the gate of NM0 is connected to VIP, so VIP becomes a negative port of the opa.

Then there's only 1 signal inversion (from NM0's gate input to VO). The amplified part from the pos. differential VIP input to VO lessens the negative gain from NM0's gate input gain to VO a bit, but it seems the latter (negative) gain is (in absolute value) higher than the positive gain from the diff. amp input. Probably due to the strong built-in negative feedback loop which i had described above, which strongly decreases the gain of the right-hand diff-amp branch.

 

[FvM]

There seems to be a misunderstanding involved with the bode diagram discussion in post #9. Phase margin has to be determined for the feedback loop gain. The feedback loop is already closed in the post #1 circuit from output node VO to inverting input.

Vip is not in the feedback loop, connecting NM0 gate to Vip or Vb respectively doesn't change the loop gain.

 

[wjxcom]

Hi all, after a long time, I come back again
Hi t4_v, Hi erikl , I connect the gate of NM0 to VB rather than VIP, and the OPA works well.
I have a question yet: my circuit is a pure DC circuit, does it mean that this circuit not need ac simulation at all? But it is a negative feedback！

 

[erikl]

I have a question yet: my circuit is a pure DC circuit, does it mean that this circuit not need ac simulation at all? But it is a negative feedback！

Your circuit is a pure DC circuit concerning your application. But you're right: as it includes feedback, it should be simulated to confirm that it is stable: open loop ac sim. for Bode diagram, and ac closed loop simulation in your real application, i.e. with stimulation & load impedances.