What's the POL (Point of Load) & Nmos LDO question

[rock_zhu]

ldo vs pol

I am confused about what's POL, and what's the relation between POL and LDO/ DC-DC?
another question, why NMOS pass element LDO is able to keep operation stability without external capcitor Cload?
Thans in advance

 

[VVV]

nmos ldo

Point of load refers to the point where the load is connected. However, the expression is mostly concerned with the point where you are sensing the output voltage of the regulator, since there are traces between the output and the actual load, so there will be voltage drops across those traces. But the voltage you are interested in is that at the load, so you talk about it, the POL voltage.
So it's not exactly the output of the regulator, but the actual point where the load gets connected to the output.

NMOS works in a follower configuration, thus the gain is 1 and there is no phase inversion. This makes the regulator "inherently stable".
For more on this take a look at this appnote: **broken link removed**

 

[rock_zhu]

ldo nmos output

Hi VVV
Thanks for you reply.
But why we involve POL circuit if it is trance as you said. what is the POL circuit?

yes, Nmos works as a follower without phase inversion but the loop is also a nagetive loop, what about the pole of this configuration?

 

[VVV]

site:edaboard.com ldo nmos

Just as I said before, the POL is simply the point where the load is connected and it is of interest because that is where the voltage should be regulated, not at the output of the regulator.

All feedback loops are negative-feedback loops, otherwise they would not do their job.
The follower presents a low output impedance, which shifts the pole of the load to higher frequency, allowing you a single-pole compensation, which is not only easy to implement, it is also inherently stable.

 

[engronger]

i just can answer you second question
when you use nmos as a pass element, the LDO's output impendance can be very small since it's a source follower, and then you can set your first pole point at the gate of pass element. so you it can stable without external capcitor Cload

but NMOS pass element LDO always has a Vgs drop , that is why most of time we use PMOS.

I am confused about what's POL, and what's the relation between POL and LDO/ DC-DC?
another question, why NMOS pass element LDO is able to keep operation stability without external capcitor Cload?
Thans in advance