Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

What's the parameters should be simulated during design VCO?

Status
Not open for further replies.

holddreams

Full Member level 6
Full Member level 6
Joined
Aug 2, 2005
Messages
351
Helped
15
Reputation
30
Reaction score
7
Trophy points
1,298
Location
Shanghai
Activity points
4,237
What's the parameters should be simulated during design VCO?

That is ,which parameters should be considered thoroughly?

THANKS.
 

Re: What's the parameters should be simulated during design

jitter and phase noise in a vco are usually the critical parameters but then it depends on your spec. what is the most stringent constraint.
 

Re: What's the parameters should be simulated during design

Hi:

If you are using LC-VCO, with MOS varactor tuning, parameters such as phase noise, VCO sensitivity, output power level, frequency pushing, frequency pulling and tuning percentage is of importance.


Rgds
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top