mady79
Member level 5
LDO Design
I am generating multiple references from a BGR output using a resistive string & pass transistor design . Refernces Vref+,Vref- & Vcm are switching at 100MHz .I am slightly confused in choosing the minimum quiecent current .I am calculating the load current based on the settling time requirement .I am deciding the output cap based on the load current requirement and also from Phase margin for the loop requirements .
Could some one let me know minimum quiecent current requirement for LDO & insight into amp bandwidth .Any paper 's ??
I am generating multiple references from a BGR output using a resistive string & pass transistor design . Refernces Vref+,Vref- & Vcm are switching at 100MHz .I am slightly confused in choosing the minimum quiecent current .I am calculating the load current based on the settling time requirement .I am deciding the output cap based on the load current requirement and also from Phase margin for the loop requirements .
Could some one let me know minimum quiecent current requirement for LDO & insight into amp bandwidth .Any paper 's ??