What's the methods to simulate Phase Noise of PLL?

[flyinspace]

phase noise mentor

I have seen some papers that suggested we can simulate PLL's PN(phase noise) by using SpectreRF (Cadence), though some limitions are exist.
My question is "Are the simulation results in SpectreRF enough accuracy if my PLL is just in MCU for clock generation(VCO's max frequency is about 80M)?"
Does anyone know how to simulate PLL's PN in SPICE,such as Hspice? If it can do that, and how about it's accuracy?
If it cannot do that, who can tell me some other methods that is competent for the work(NOTE: based on PLL's transistor level circuit, not behavior model) ?
Thanks a lot!
Best Regard!

 

[PaulHolland]

Hi,

You can calculate the phase noise of your PLL very simple. What is your loop BW ??.. Your Ref Freq. and do you have the Phase Noise performance of your XTAL Osc ?.. What is your divider ratio, I mean VCO/N = Comp Freq. What is your Phase Noise performance of your VCO without PLL loop control ?.

If you know all these you can make a plot of the resulted Phase Noise, all Phase Noise inband (In loop BW of PLL) will be equal to Phase Noise of XTAL + 20Log N and the Phase Noise outside the Loop BW will be the same as your VCO without PLL control.

hope this helps,
Paul.

PS: I know that we don't 'take all the parametrs into account but the most important are here !.

 

[flyinspace]

PaulHolland:
My meaning is to find a method to simulate the PN of PLL based on transistor level in circuit simulator such as SPICE.
Do you have a good method?
Thank you!

 

[PaulHolland]

Hi,

Why on transistor level ???.. The main component in final PN I already gave you the rest if of minor importance in most cases unless you are making a system with a PN of -140 dBc...

regards,

Paul.

 

[tlihu]

Sometimes we need to know/consider the non-ideal factory of a design.

 

[flyinspace]

Hi,

Why on transistor level ???.. The main component in final PN I already gave you the rest if of minor importance in most cases unless you are making a system with a PN of -140 dBc...

regards,

Paul.

Paul,
Finding a method of simulating PN on transistor level is my research project which is my mentor's order. So I have to do that.
Your meaning is unnecessary to simulate PN on transistor level? And can SPICE do that, if I have to do that on transistor level?
Just like what you have said, when I have known the VCO structure such as relaxation oscillator, how can I simulate its PN by SPICE?
I do appreciate for your help!!
Best Regard!
Vincent

 

[khouly]

i think ordinary spice simulators cannot simulate phase noise performance of the pll
some simulators with RF cababilities , can like specterRF , ELDORF, ADS2002, 2003 can do the job also

 

[amitbhaiji]

With hspice we cannot simulate the phase noise. But one can use hspice to simulate the transistor level jitter ( Both long term and shot term jitter using the eye diagram plot). and then using some mathamatical modelling and intepolation be can obtained the phase noise plot of either the pll or the oscillator.

Amit

 

[cretu]

With hspice we cannot simulate the phase noise. But one can use hspice to simulate the transistor level jitter ( Both long term and shot term jitter using the eye diagram plot). and then using some mathamatical modelling and intepolation be can obtained the phase noise plot of either the pll or the oscillator.

Amit

Hi tehre

Do u have by any chance a behavioural model for a pll? Or an eye diagram generator for hspice? I would really appreciate any info about that

cretu

 

[amitbhaiji]

WEll as such i dont have any behavioral model for pll. But for plotting an eye diagram this is the simple prodecure.
1) Plug an perodic ramp source of same frequency as the output frequency of pll (be careful while putting the frequency) between gnd and dummy node. Run your simple transient analyis simulation in hspice.
2) Then in your waveform viewer plot the output of the pll with respect to the ramp source and what you are seeing is the eye diagram.
3) You can measure both the short term and long term jitter by making the frequency of ramp source integral multiple of the output frequency..

AMit

 

[savithru]

Dear Amith
you wrote.. Then in your waveform viewer plot the output of the pll with respect to the ramp source and what you are seeing is the eye diagram
Can you pls explain me what is "plot the output of the pll with respect to the ramp source" meanse.

sorry it may look silly, but I want to know what it is. The problem I am facing in simulating the longterm jitter ( Accumulated jitter over 20us) is that I am unable to align the refernce signal and my PLL/VCO output signal.

Also ..

If I simulate my VCO for 20us for phase noise and calulate the Cycle to Cycle Jitter, does this give me the Long term jitter.

pls reply.

 

[RDRyan]

i think ordinary spice simulators cannot simulate phase noise performance of the pll
some simulators with RF cababilities , can like specterRF , ELDORF, ADS2002, 2003 can do the job also

Can we save the VCO oscillation wave, use matlab to calculate the spectrum of the wave. and then calcule the Phase Noise?

I am also faced with the problem of how to simulation the Phase Noise. Above is my idea, I don't know whether is it feasible.

 

[layes2]

hspice SNOISE or spectre pss can do that

 

[mists]

a very good ppt for PLL simulation using hspice-rf

 

[horzonbluz]

Is it a training manual of Hspice RF?
If it was the one i need, thanks a lot.

 

[koto135]

if y simulate in cadence . i think pniose and pss can be used.

 

[zyyang]

for the clock generator, may be we consider on the jitter more, but if you must pay attention to PN, may be there is no business simulator for simulate the phase noise of pll. you should simulator the phase noise of sub-modules like pfd+charge pump, loop filter, vco, reference and divider, then use the mathmatical model(not linearity) to calulate the whole phase noise. By the way, the phase noise of sub-modules can be simulated by hspiceRF if you must use spice.
Regards

 

[johnq_hu]

for the clock generator, may be we consider on the jitter more, but if you must pay attention to PN, may be there is no business simulator for simulate the phase noise of pll. you should simulator the phase noise of sub-modules like pfd+charge pump, loop filter, vco, reference and divider, then use the mathmatical model(not linearity) to calulate the whole phase noise. By the way, the phase noise of sub-modules can be simulated by hspiceRF if you must use spice.
Regards

Then how could you simulate the jitter? I mean different input clock and different power supply lead to different PLL jitter result. How could you apply these stimulus to get the jitter result? especially for LONG TERM JITTER.

 

[AdvaRes]

What about characterization of the PLL and the VCO ?
Is there any elaborated material ?

 

[Sadegh.j]

I am using ADS, measuring phase noise with ADS is quite easy. tell me if you need any more data