What's the function of phase_lin statements in VerilogA?

[flyinspace]

Hi

I find a VCO from Cadence AHDL library, just as:
-------------------------------------------------------------------
module vco(vin, vout);
input vin;
output vout;
electrical vin, vout;
parameter real vco_amp = 1.0 from (0:inf);
parameter real vco_cf = 1500.0 from (0:inf);
parameter real vco_gain = 1000.0K exclude 0.0;
parameter integer vco_ppc = 40 from [4:inf);

real wc; // center freq in rad/s
real phase_lin; // wc*time component of phase
real phase_nonlin; // the idt(k*f(t)) of phase
integer num_cycles; // number of cycles in linear phase component
real inst_freq; // instanteous frequency

analog begin

@ ( initial_step ) begin
wc = `M_TWO_PI * vco_cf;
end

//
// linear portion is calculated so that it remains in the +/- 2`PI range
// This is to ensure it's value doesn't get too large and cause rounding
// problems for calculation of the phase.
//
phase_lin = wc * $abstime;
num_cycles = phase_lin / `M_TWO_PI;
phase_lin = phase_lin - num_cycles * `M_TWO_PI;

phase_nonlin = `M_TWO_PI * vco_gain * idtmod ( V(vin), 0, 1000.0, 0.0);

V(vout) <+ vco_amp * sin (phase_lin + phase_nonlin);

//
// ensure that modulator output recalculated soon.
//
inst_freq = vco_cf + vco_gain * V(vin);
$bound_step (1/(vco_ppc * inst_freq));
end
endmodule
-------------------------------------------------------------------
My question is what 's the function of BLUE statements? It seems phase_lin = 0 !
Who can tell me the reason?

Thanks in advance!

 

[srik]

vco veriloga

The comments above the blue lines explain its purpose!

Those lines are to prevent phase ramping to very high value with time.This is because the simulator cannot deal with a very large numerical value. So it wraps the phase to +/- 2pi.

srik