What's the drawback of MOSFET cap for miller compensation

[ricklin]

Hi, All
I've designed a buffer for a reference voltage in standard CMOS process. The buffer used a 2-stage miller compensation opamp followed a source follower (the follower feed back to opamp neg), and the output is a follower replica.

My problem is that if using MOSFET as the compensation cap, I can save area and big metal wire pathes ( If use MOM caps, the metal line esp power and ground will be blocked). As a replica architecture, the feedback loop itself is seldom disturbed.

So what's the drawback of MOSFET compensation? Especially that can not be shown by simulations both AC and tran.

Best Regards

 

[pixel]

Re: What's the drawback of MOSFET cap for miller compensatio

How do you conect mosfet as a capacitance?

 

[ricklin]

Re: What's the drawback of MOSFET cap for miller compensatio

How do you conect mosfet as a capacitance?

PMOS cap, gate at the 2nd stage input ( an NMOS gate), source drain and N-well shorted to connect the 2nd stage output.

Any comments or suggestion? Thanks

 

[drDOC]

Drawbacks of a MOSCAP in contrast to Metal on Metal are:

1 Voltage non linearity
2 Paracitic substrate capacitor

But the benefit is AREA

The non linearity is not a big problem for a miller cap. You should only be sure that the amp has phase margin when the miller cap is biased to be it's smallest value, or be sure it never is biased to be small.

You can check if the non linearity is modeled by building a RC low pass and see the corner frequency shift by applying different DC operating points.

And you can place the substrate cap at the output, because then it only loads the output a bit.

 

[standup]

Hi，drDOC：
I can't understand what the "Paracitic substrate capacitor " is, can you explain it for me?

 

[dick_freebird]

The other drawback of a MOSFET is that its capacitance
swings with applied voltage - big time, if you are in a fully
depleted technology, significantly in any case. So while
you may be able to hit your phase margin stability goal,
large-signal AC signals will see distortion introduced.
There is a possibility that at one common-mode output
voltage you might be stable because the capacitance is high
(enhancement mode) and at the other end you are unstable
because the capacitance has swung to minimum (depletion).

Approaches include back-to-back MOS caps (so that one or
the other is always at or near max), use of depletion-
mode (always-enhanced) MOSFETs, or attaching the cap
to nodes which are always certain to impose the desired
polarity to the gate oxide.

 

[snafflekid]

Re: What's the drawback of MOSFET cap for miller compensatio

Hi，drDOC：
I can't understand what the "Paracitic substrate capacitor " is, can you explain it for me?

The top plate of your capacitor is the gate of the PMOS. The bottom plate is the conductive channel created under the gate due to accumulation. However there is the consideration of the substrate capacitance. The PMOS body is n-type sitting in a p-type substrate. The substrate is connected to ground and that creates a parasitic junction capacitance between the bottom plate and ground. If you drive the bottom plate with a low output impedance, the pole created by the low output impedance and the junction capacitor is high enough to ignore.