what's the difference between these two circuits?

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what's the difference between these two circuits?
And when and where these circuits will be used?
 

hello!
1-in circuit a and b drain voltages supply is same
2-in a gate supply is for drain term,inal of m1 and m4, while in b the input is for m3 and m4
3-in a m4 and m1 is draining by the in, while in b m3 and m4 ars draining by the in
 

Threshold will be different.
Let suppose Vthp = Vthn and neglect body effect.
For (a) threshold will be vdd/2 (when PMOS current is equal to NMOS current).
For (b) threshold will be (vdd-2*Vthp)/2 or vdd/2-Vthp.
 

I think the input range is different.
 

Hi,

In circuit A...VIH will be equal to that of the normal invertor. Since, minimum input voltage to push the PMOS to cutoff will be around 4V (assuming 5V as supply and Vth as 1V).

Whereas in circuit B there will be 2 Vt drops at the source of Input PMOS, hence assume it as 3V. Hence any voltage above 2v will push the PMOS into cutoff and hence VIH is less in that of circuit A.

Both VOH is less than 2Vt. Hence both ciruicts have lower noise margin.

But the circuit B should be faster than CircuitA ,Since as the input arrives Circuit B should charge only one node but circuit A should charge 3 nodes.

Hope this helps.

Regards,
Prakash
 

Both VOH is less than 2Vt. Hence both ciruicts have lower noise margin.


Thanks a lot.
Why do you say “Both VOH is less than 2Vt”？
Does it mean that VOH=VDD-3Vt=2Vt(assuming that VDD=5V,Vt=1V)?
 

Hi,

Since in both the circuits we have diode connected Transistors (two), there is atleast Vt drop in these transistors.

Hence the output node will be always less than Vdd-2Vt (in our case 5-2*1=3V)

This is to get an rough idea, but my take on the circuits is, it will be always less than 3V. there by reducing the noise margin.

Prakash.
 

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