What's the CCOpt replacement for bufferTreeSynthesis?

[digitalo]

Hi all,

in our old INNOVUS flow, we used bufferTreeSynthesis to create buffer trees for high fanout nets, e.g. the async. reset.

Now we are in the process of migrating to CCOpt, and I cannot find a suitable alternative. I considered skew groups or H trees, but neither seems to be what we need.

What we need is a way to define a maximum delay and a maximum skew for a net that is not a clock net and does not originate at a module input pin. The latter is where create_clock_tree fails if that's the command to use: I can define a clock tree for -source RESET, which is the module's reset input, but not for -source sync/RESET (or any other way to name the pin that I can think of) which is the output of the reset synchronization logic.

Thanks,
digitalo

 

[ThisIsNotSam]

My understanding is that regular optDesign takes care of high fanout nets.

edit: try to check if optDesign respects the skew/delay constraints you put on the nets. It should. I think I have done that in a previous tapeout to integrate analog and digital.

 

[digitalo]

My understanding is that regular optDesign takes care of high fanout nets.

It sure does. But not in the way I want it. I certainly do need more control over what's happening.

edit: try to check if optDesign respects the skew/delay constraints you put on the nets. It should. I think I have done that in a previous tapeout to integrate analog and digital.

But how should I specify a skew constraint for a single net? I need to refer to a group of nets for a sensible definition of skew.

digitalo

 

[ThisIsNotSam]

I have looked into the create_ccopt_skew_group command, it doesn't do what you want. Not sure. Here is a wild guess. I think you can specify the behavior you want using the old clock tree format from Encounter CTS days. Innovus still reads that file format and transforms that to its internal ccopt targets and configurations. Maybe that process will give you some hint of how to proceed.

 

[digitalo]

I don't know if I'm making progress or heading straight into a dead end:
For single signals where I need to constrain the skew, creating a skew group from the source pin in questions gives messages to suggest that creating a clock tree might be in order. So I create a clock tree instead of a skew group, and the skew group is automatically created.
I can set the constraints I require, but they are ignored.

Looking into the database, I can see that all pins are ignored, i.e. in .cts_sinks, but not in .cts_active_sinks.
When creating the clock tree, I get
Found 78 implicit ignore or stop or exclude pins - run report_clock_trees -list_special_pins for more details.
So I run the command as suggested to get
test_I/g1060__3377/SEL implicit ignore
and
test_I/sclk_reg[0]/D implicit exclude

So I "just" need to find out why the pins are ignored. The obvious answer is "because they are not clock inputs". These are multiplexer select pins.

I'm looking through the help and database properties, but so far failed to come up with the solution. cts_ignore_pins sounds interesting, but is empty.

digitalo

- - - Updated - - -

OK, this seems to work: I try to force all connected pins to the "stop" sink type.

create_clock_tree_spec

set_db net:TEST .loads.cts_sink_type stop
create_clock_tree -source TEST
set_db skew_group:TEST .cts_target_skew 0.2

I still have to check in detail how the real case looks, but at least I get a sensible tree and a skew report.