guybrush
Junior Member level 3
SERIAL RECEIVER
I'm designing an ACTEL A54SX FPGA for control and monitoring of a power board, implementing two serial interfaces very slow (19200 bit/s, with parity) and some digital I/O. On the board i have a 8MHz clock, so I have to divide it down to 8x19200, that will be the higest frequency in the serial receiver.
This are my different solutions:
1) I use the 8MHz clock as HCLK, all design is synchronous and I produce the CE for 19200 and 8x19200 using suitable counters.
2) I divide the 8MHz system clock down to 8x19200, the output of this counter will be the clock used into the FPGA routed with CLKA or CLKB.
3) I use the CLKA input for the 8MHz system clock, I divide down the frequency to 8x19200 that is routed out of the FPGA and then back thru HCLK. Then synchronuos design.
Which is the best solution in your opinion?
I'm designing an ACTEL A54SX FPGA for control and monitoring of a power board, implementing two serial interfaces very slow (19200 bit/s, with parity) and some digital I/O. On the board i have a 8MHz clock, so I have to divide it down to 8x19200, that will be the higest frequency in the serial receiver.
This are my different solutions:
1) I use the 8MHz clock as HCLK, all design is synchronous and I produce the CE for 19200 and 8x19200 using suitable counters.
2) I divide the 8MHz system clock down to 8x19200, the output of this counter will be the clock used into the FPGA routed with CLKA or CLKB.
3) I use the CLKA input for the 8MHz system clock, I divide down the frequency to 8x19200 that is routed out of the FPGA and then back thru HCLK. Then synchronuos design.
Which is the best solution in your opinion?