library IEEE;
use IEEE.std_logic_1164.all;
entity fsm is
port (
clk, reset : IN std_logic;
input :in std_logic_vector(1 downto 0);
sum : OUT std_logic);
end entity;
architecture beh1 of fsm is
type state_type is (s1,s2);
signal state, next_state: state_type;
signal i_input: std_logic_vector(1 downto 0);
begin
sequential_process: process (clk, reset)
begin
if (reset ='1') then
state<=s1;
elsif (clk = '1' and clk'Event) then
state <= next_state;
i_input<=input;
end if;
end process sequential_process;
nextstate_process : process (state,i_input)
begin
case state is
when s1 =>
if i_input="00" then
next_state <= s1;
elsif i_input="01" then
next_state<=s1;
elsif i_input="10" then
next_state<=s1;
elsif i_input="11" then
next_state <= s2;
end if;
when s2 =>
if i_input="00" then
next_state <= s1;
elsif i_input="01" then
next_state<=s2;
elsif i_input="10" then
next_state<=s2;
elsif i_input="11" then
next_state <= s2;
end if;
end case;
end process nextstate_process;
output_process : process (state,i_input)
begin
case state is
when s1 =>
if i_input="00" then
sum<='0';
elsif i_input="01" then
sum<='1';
elsif i_input="10" then
sum<='1';
elsif i_input="11" then
sum<='0';
end if;
when s2 =>
if i_input="00" then
sum<='1';
elsif i_input="01" then
sum<='0';
elsif i_input="10" then
sum<='0';
elsif i_input="11" then
sum<='1';
end if;
end case;
end process output_process;
end beh1;
library IEEE;
use IEEE.std_logic_1164.all;
entity fsm is
port (
clk, reset : in std_logic;
input : in std_logic_vector(1 downto 0);
sum : out std_logic);
end entity;
architecture beh1 of fsm is
type state_type is (s1, s2);
signal state, next_state : state_type;
signal i_input : std_logic_vector(1 downto 0);
begin
sequential_process : process (clk, reset)
begin
if (reset = '1') then
state <= s1;
i_input <= (others => '0');
elsif (clk = '1' and clk'event) then
state <= next_state;
i_input <= input;
end if;
end process sequential_process;
nextstate_process : process (state, i_input)
begin
case state is
when s1 =>
if i_input = "11" then
next_state <= s2;
else
next_state <= state;
end if;
when s2 =>
if i_input = "00" then
next_state <= s1;
else
next_state <= state;
end if;
when others => null;
end case;
end process nextstate_process;
output_process : process (state, i_input)
begin
case state is
when s1 =>
sum <= i_input(0) xor i_input(1);
when s2 =>
sum <= not (i_input(0) xor i_input(1));
when others => null;
end case;
end process output_process;
end beh1;
library IEEE;
use IEEE.std_logic_1164.all;
entity fsm is
port (
clk, reset : IN std_logic;
input :in std_logic_vector(1 downto 0);
i_sum : OUT std_logic);
end entity;
architecture beh1 of fsm is
type state_type is (s1,s2,s3);
signal state, next_state: state_type;
--signal i_sum: std_logic;
signal i_input: std_logic_vector(1 downto 0);
begin
sequential_process: process (clk, reset)
begin
if (reset ='1') then
state<=s1;
elsif (clk = '1' and clk'Event) then
state <= next_state;
i_input<=input;
-- end if;
-- if (clk='0' and clk'event) then
-- sum<=i_sum;
end if;
end process sequential_process;
nextstate_process : process (state,i_input)
begin
case state is
when s1 =>
if i_input="00" then
next_state <= s1;
elsif i_input="01" then
next_state<=s1;
elsif i_input="10" then
next_state<=s1;
elsif i_input="11" then
next_state <= s2;
else
next_state<= s1;
end if;
when s2 =>
if i_input="00" then
next_state <= s1;
elsif i_input="01" then
next_state<=s2;
elsif i_input="10" then
next_state<=s2;
else
next_state <= s2;
end if;
when s3=> next_state<=s3;
end case;
end process nextstate_process;
output_process : process (state,i_input)
begin
case state is
when s1 =>
if i_input="00" then
i_sum<='0';
elsif i_input="01" then
i_sum<='1';
elsif i_input="10" then
i_sum<='1';
elsif i_input="11" then
i_sum<='0';
else
i_sum<='0';
end if;
when s2 =>
if i_input="00" then
i_sum<='1';
elsif i_input="01" then
i_sum<='0';
elsif i_input="10" then
i_sum<='0';
elsif i_input="11" then
i_sum<='1';
else
i_sum<='1';
end if;
when s3=> i_sum<='0';
end case;
end process output_process;
end beh1;
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <fsm>.
Related source file is "c:/qomqom/FSMAs.vhd".
INFO:Xst:1799 - State s3 is never reached in FSM <state>.
Found finite state machine <FSM_0> for signal <state>.
-----------------------------------------------------------------------
| States | 2 |
| Transitions | 7 |
| Inputs | 4 |
| Outputs | 2 |
| Clock | clk (rising_edge) |
| Reset | reset (positive) |
| Reset type | asynchronous |
| Reset State | s1 |
| Power Up State | s1 |
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 2-bit register for signal <i_input>.
Summary:
inferred 1 Finite State Machine(s).
inferred 2 D-type flip-flop(s).
Unit <fsm> synthesized.
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <state[1:1]> with gray encoding.
-------------------
State | Encoding
-------------------
s1 | 0
s2 | 1
s3 | unreached
-------------------
Dynamic shift register inference ...
=========================================================================
HDL Synthesis Report
Macro Statistics
# FSMs : 1
# Registers : 2
1-bit register : 1
2-bit register : 1
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <fsm> ...
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx.
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block fsm, actual ratio is 0.
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : fsm.ngr
Top Level Output File Name : fsm
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 5
Macro Statistics :
# Registers : 1
# 2-bit register : 1
Cell Usage :
# BELS : 3
# INV : 1
# LUT3 : 1
# LUT3_L : 1
# FlipFlops/Latches : 3
# FDC : 1
# FDE : 2
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 4
# IBUF : 3
# OBUF : 1
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s200ft256-4
Number of Slices: 2 out of 1920 0%
Number of Slice Flip Flops: 3 out of 3840 0%
Number of 4 input LUTs: 2 out of 3840 0%
Number of bonded IOBs: 5 out of 173 2%
Number of GCLKs: 1 out of 8 12%
=========================================================================
module top (clk, reset, inputs, sum);
input clk, reset;
input [1:0] inputs;
reg state;
output sum;
assign sum = ^{state,inputs};
always @ (posedge clk) begin
state <= reset ? 0 : (inputs == 'b11) ? 1 : (inputs == 'b00) ? 0 : state;
end
endmodule
Selected Device : 2v80fg256-4
Number of Slices: 1 out of 512 0%
Number of Slice Flip Flops: 1 out of 1024 0%
Number of 4 input LUTs: 2 out of 1024 0%
Number of bonded IOBs: 5 out of 120 4%
Number of GCLKs: 1 out of 16 6%
nand_gates said:Here I have re-written the code!
Hope this helps you understand how to use VHDL!
Code:nextstate_process : process (state, i_input) begin case state is when s1 => if i_input = "11" then next_state <= s2; else next_state <= state; end if; when s2 => if i_input = "00" then next_state <= s1; else next_state <= state; end if; when others => null; end case; end process nextstate_process; output_process : process (state, i_input) begin case state is when s1 => sum <= i_input(0) xor i_input(1); when s2 => sum <= not (i_input(0) xor i_input(1)); when others => null; end case; end process output_process; end beh1;
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