What's the advantage of writing VHDL that can be recognized

[cmos babe]

vhdl advantage

What's the advantage of writing VHDL that can be recognized (inferred) by XST ? I wrote a VHDL program describing a finite state machine, I tried to write it as suggested by the XST guide but it wasn't recognized as an FSM ... does it mean i should change the program till an FSM is inferred?

 

[echo47]

info xst 1799 state unreached

If XST recognizes the FSM, you may get a faster or smaller design. Depending on your goals, that may be worthwhile.

Can you post your code here? Maybe someone can see the problem.

 

[luancao]

Re: What's the advantage of writing VHDL that can be recogni

Generally speaking, the synthesizable style VHDL could be synthesised by a synthesizer. And the behavioral description VHDL could be recogized by simulator only...

I could not catch your key points. You could describe in detail.

 

[cmos babe]

Re: What's the advantage of writing VHDL that can be recogni

The code describes a Mealy FSM serial adder as shown in state diagram..

library IEEE;
use IEEE.std_logic_1164.all;	

entity fsm is
port (
clk, reset : IN std_logic;
input :in std_logic_vector(1 downto 0);
sum : OUT std_logic);
end entity;

architecture beh1 of fsm is
type state_type is (s1,s2);
signal state, next_state: state_type;

signal i_input: std_logic_vector(1 downto 0);
begin
	
sequential_process: process (clk, reset)
begin
		if (reset ='1') then
		state<=s1;
		elsif (clk = '1' and clk'Event) then
		state <= next_state;
 		i_input<=input;
end if;
end process sequential_process; 

 nextstate_process : process (state,i_input)
begin
case state is
			when s1 =>
				if i_input="00" then
				next_state <= s1;
				elsif i_input="01" then
					next_state<=s1;
				elsif i_input="10" then
					next_state<=s1;
					elsif i_input="11" then
				next_state <= s2;
				end if;
			when s2 =>
				if i_input="00" then
				next_state <= s1;
				elsif i_input="01" then
					next_state<=s2;
				elsif i_input="10" then
					next_state<=s2;
					elsif i_input="11" then
				next_state <= s2;
				end if;
			
end case;
end process nextstate_process;

output_process : process (state,i_input)
	begin
		case state is
			when s1 => 
				if i_input="00" then
				sum<='0';
				elsif i_input="01" then
				sum<='1';
				elsif i_input="10" then
				sum<='1';
				elsif i_input="11" then
			                sum<='0';							 
			end if;
			when s2 =>		
				if i_input="00" then
				sum<='1';
				elsif i_input="01" then
				sum<='0';
				elsif i_input="10" then
				sum<='0';
				elsif i_input="11" then
			                sum<='1';
			 end if;							  
end case;
end process output_process;
end beh1;

 

[echo47]

I don't know VHDL very well. Are you hoping to create a fully synchronous design? The HDL Synthesis report is emitting warnings about latches. XST won't infer FSM in asynchronous logic.

 

[tkbits]

Re: What's the advantage of writing VHDL that can be recogni

XST is not inferring an FSM because you have only two states. Add a third state, and it will infer an FSM.

In the case of an FSM, inferring it allows you to choose the kind of FSM. For example, XST will normally choose one-hot encoding, which is not directly coded in your example. Under Synthesis properties, HDL options, you can select a different kind of FSM.

 

[echo47]

I see what's causing the synthesis "latch" warnings (I'm using ISE 7.1.03i).
Change your four-way "if" statements so the last one is an "else". XST is sometimes fussy about little things like that.

You're right tkbits. There's only one flop in the whole design.

 

[dBUGGER]

Hi,
to prevent inferring latches make sure the last statement in the if-elsif structure is an ELSE statement. If it's an elsif then XST surely will infer a latch. And what i see is that even output_process seems to be redundant. You can keep the SUM o/p in the nextstate_process itself. Just try that.

Best Regards,

 

[adap]

You should use the (when others =>) in the case statement. This also creates latches.

 

[nand_gates]

Re: What's the advantage of writing VHDL that can be recogni

Here I have re-written the code!
Hope this helps you understand how to use VHDL!

library IEEE;
use IEEE.std_logic_1164.all;

entity fsm is
  port (
    clk, reset : in  std_logic;
    input      : in  std_logic_vector(1 downto 0);
    sum        : out std_logic);
end entity;

architecture beh1 of fsm is
  type state_type is (s1, s2);
  signal state, next_state : state_type;

  signal i_input : std_logic_vector(1 downto 0);
begin

  sequential_process : process (clk, reset)
  begin
    if (reset = '1') then
      state   <= s1;
      i_input <= (others => '0');
    elsif (clk = '1' and clk'event) then
      state   <= next_state;
      i_input <= input;
    end if;
  end process sequential_process;

  nextstate_process : process (state, i_input)
  begin
    case state is
      when s1 =>
        if i_input = "11" then
          next_state <= s2;
        else
          next_state <= state;
        end if;
      when s2 =>
        if i_input = "00" then
          next_state <= s1;
        else
          next_state <= state;
        end if;
      when others => null;
    end case;
  end process nextstate_process;

  output_process : process (state, i_input)
  begin
    case state is
      when s1 =>
        sum <= i_input(0) xor i_input(1);
      when s2 =>
        sum <= not (i_input(0) xor i_input(1));
      when others => null;
    end case;
  end process output_process;
end beh1;

 

[tkbits]

Re: What's the advantage of writing VHDL that can be recogni

XST still doesn't infer an FSM, unless you're using an option I'm not aware of.

Two-way CASE is equivalent to IF-THEN-ELSE, so after that optimization, the result does not look like an FSM to XST.

 

[cmos babe]

Re: What's the advantage of writing VHDL that can be recogni

library IEEE;
use IEEE.std_logic_1164.all;	

entity fsm is
port (
clk, reset : IN std_logic;
input :in std_logic_vector(1 downto 0);
i_sum : OUT std_logic);
end entity;

architecture beh1 of fsm is
type state_type is (s1,s2,s3);
signal state, next_state: state_type;
--signal i_sum: std_logic;
signal i_input: std_logic_vector(1 downto 0);
begin
	
sequential_process: process (clk, reset)
begin
		if (reset ='1') then
		state<=s1;
		elsif (clk = '1' and clk'Event) then
		state <= next_state;
 		i_input<=input;
--		end if;
--		if (clk='0' and clk'event) then
--		sum<=i_sum;
end if;
end process sequential_process; 

 nextstate_process : process (state,i_input)
begin
case state is
			when s1 =>
				if i_input="00" then
				next_state <= s1;
				elsif i_input="01" then
					next_state<=s1;
				elsif i_input="10" then
					next_state<=s1;
					elsif i_input="11" then
				next_state <= s2;
				   else 
				next_state<= s1;
				end if;
			when s2 =>
				if i_input="00" then
				next_state <= s1;
				elsif i_input="01" then
					next_state<=s2;
				elsif i_input="10" then
					next_state<=s2;
					else
				next_state <= s2;
				end if;							
				when s3=> next_state<=s3;
			
end case;
end process nextstate_process;

output_process : process (state,i_input)
	begin
		case state is
			when s1 => 
				if i_input="00" then
				i_sum<='0';
				elsif i_input="01" then
						i_sum<='1';
				elsif i_input="10" then	
						i_sum<='1';
						elsif i_input="11" then
						i_sum<='0';	  
					else
			i_sum<='0';							 
			end if;
			when s2 =>		
				if i_input="00" then
				i_sum<='1';
				elsif i_input="01" then
						i_sum<='0';
				elsif i_input="10" then
				i_sum<='0';	
					elsif i_input="11" then
						i_sum<='1';	  	  
					else
			i_sum<='1';
			 end if;		
			 when s3=> i_sum<='0';			  
end case;
end process output_process;
end beh1;

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <fsm>.
    Related source file is "c:/qomqom/FSMAs.vhd".
INFO:Xst:1799 - State s3 is never reached in FSM <state>.
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 2                                              |
    | Transitions        | 7                                              |
    | Inputs             | 4                                              |
    | Outputs            | 2                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | reset (positive)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | s1                                             |
    | Power Up State     | s1                                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 2-bit register for signal <i_input>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   2 D-type flip-flop(s).
Unit <fsm> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <state[1:1]> with gray encoding.
-------------------
 State | Encoding
-------------------
 s1    | 0
 s2    | 1
 s3    | unreached
-------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Registers                        : 2
 1-bit register                    : 1
 2-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <fsm> ...
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block fsm, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : fsm.ngr
Top Level Output File Name         : fsm
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 5

Macro Statistics :
# Registers                        : 1
#      2-bit register              : 1

Cell Usage :
# BELS                             : 3
#      INV                         : 1
#      LUT3                        : 1
#      LUT3_L                      : 1
# FlipFlops/Latches                : 3
#      FDC                         : 1
#      FDE                         : 2
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 4
#      IBUF                        : 3
#      OBUF                        : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                       2  out of   1920     0%  
 Number of Slice Flip Flops:             3  out of   3840     0%  
 Number of 4 input LUTs:                 2  out of   3840     0%  
 Number of bonded IOBs:                  5  out of    173     2%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================

I added a third state and put an ELSE in the end like tkbits and echo suggested.

 

[echo47]

That seems like a lot of work. Is that typical for VHDL? Perhaps it's an academic project to learn FSM.
In Verilog I would do something like this (untested):

module top (clk, reset, inputs, sum);
  input           clk, reset;
  input     [1:0] inputs;
  reg             state;
  output          sum;

  assign sum = ^{state,inputs};

  always @ (posedge clk) begin
    state <= reset ? 0 : (inputs == 'b11) ? 1 : (inputs == 'b00) ? 0 : state;
  end
endmodule

Selected Device : 2v80fg256-4

 Number of Slices:                       1  out of    512     0%
 Number of Slice Flip Flops:             1  out of   1024     0%
 Number of 4 input LUTs:                 2  out of   1024     0%
 Number of bonded IOBs:                  5  out of    120     4%
 Number of GCLKs:                        1  out of     16     6%

 

[cmos babe]

Re: What's the advantage of writing VHDL that can be recogni

yeah this project is for educational purpose and i will do more exercises like this before i start working on a real project...I think the code can be more combact by using two processes instead of three ...your verilog code looks attractive 8O I may learn verilog too..

My next plan now is to complete this educational design by adding two parallel-in/serial-out shift registers whose outputs (SO pins) are connected to the inputs of this serial adder FSM , and an output serial-in/parallel-out shift register.. And then I want to build a controller (Another FSM) that will generate the control signals which are the reset singal for the serial adder ,Synchronous_Parallel_Load signals for the input shift registers.

My questions now:
1-How can the controller know that eight bits have been shifted and the result is ready in the output register,is an 8-bit counter a solution ? (remember this is an educational project)

2-When should the synchronous_load signals be generated ? I think that if the controller generates them at a positive edge ,the register won't be able to detect it and the byte won't be loaded .. I don't know if what i'm saying is correct or not ..HELP :|

 

[tkbits]

Re: What's the advantage of writing VHDL that can be recogni

1) Yes, a counter will work very well. 8-bits will allow you to count to 255, so that is a bit of an overkill.

2) The synchronous load signal must be generated in the clock cycle preceding the update edge. So far, it seems to me that registers (or counters) are always loaded on a state transition. So my solution has been to set the load enable on a transition condition. It isn't necessary to register it.

 

[presto]

Re: What's the advantage of writing VHDL that can be recogni

Here I have re-written the code!
Hope this helps you understand how to use VHDL!

  nextstate_process : process (state, i_input)
  begin
    case state is
      when s1 =>
        if i_input = "11" then
          next_state <= s2;
        else
          next_state <= state;
        end if;
      when s2 =>
        if i_input = "00" then
          next_state <= s1;
        else
          next_state <= state;
        end if;
      when others => null;
    end case;
  end process nextstate_process;

  output_process : process (state, i_input)
  begin
    case state is
      when s1 =>
        sum <= i_input(0) xor i_input(1);
      when s2 =>
        sum <= not (i_input(0) xor i_input(1));
      when others => null;
    end case;
  end process output_process;
end beh1;

I'm not sure if it's reliable to simply use "when others => null", because as long as there is one state missing in the "when" list, this will pretty sure to infer a latch.

In my habit, I usually set "when other =>" to generate a default reset in the sequencial part, e.g. "when others => next_state <= s1;", sometimes an error assertion as well; and in the combinational part I set default value right after the "begin", e.g. "begin ... sum <= (others => '0'); ... case ...".

Please, let me know if I'm wrong.

 

[zlop]

Re: What's the advantage of writing VHDL that can be recogni

[quote="presto]I'm not sure if it's reliable to simply use "when others => null", because as long as there is one state missing in the "when" list, this will pretty sure to infer a latch.

In my habit, I usually set "when other =>" to generate a default reset in the sequencial part, e.g. "when others => next_state <= s1;", sometimes an error assertion as well; and in the combinational part I set default value right after the "begin", e.g. "begin ... sum <= (others => '0'); ... case ...".

Please, let me know if I'm wrong.[/quote]
In VHDL, the CASE statement's default branch is NOT imposed by the IEEE standard. It's "SUGGESTED". In synthesisable coding style, the process method of "default" depends upon the synthesis tool you use. Some need it, and some dont. The content of "default" must be chosen carefully. It must not endanger your project. In your case, if the defualt process dose not harm your goal of the project, you can either write or not, of course what you write is not important too.