What's shadow logic of memories?

[yuhiub90]

Hi guys, I'd like to kow what's exactly shadow logic around memories. I'm learning Memory BIST. It mention testing method for shadow logic and I don't know what it is.
Thanks!

 

[swethapr565]

Hi,
DFT shadow logic is recommended to increase the testability of logic around modules for which the ATPG tools cannot generate test patterns. Shadow logic adds the ability to
(i) Observe the data on the nets connected to the inputs of the untestable logic
(ii) Control the nets connected to the outputs of the untestable logic
There are two ways to insert shadow logic:

1 ) Manually Inserting DFT Shadow Logic
The manual method supports insertion of bypass logic and scannable logic with or without register sharing.

2) Automatically Inserting DFT Shadow Logic
The automatic method only supports insertion of scannable logic without register sharing.

now, if there is any ATPG- untestable module( in your case RAM), RAM can be untestable due to many reasons for example, it could be acting as blackbox and hence is untestable at the inputs and the outputs i.e., not observable and not controllable then you call that portion as untestable shadow logic region. so you need to insert a dft shadow logic in order to observe and control the inputs of RAM.

If your design has some modules for which the ATPG tools cannot generate test patterns, you can increase the testability of the logic around these modules by inserting DFT shadow logic. You can also insert control and observation test points to improve the testability of your design. shadow logic is inserted around the instances(RAM) whose pins are the source of the violations.Violations are fixed for logic abstract models and timing_models whose instances have known pin directions. As the pin directions of the modules must be known to properly insert the shadow logic, the modules must be described as either a whitebox (netlist representation), as a logic abstract (empty module with I/O port declarations), or represented as a cell reference (timing_model) in Liberty format.
For example, the logic before a RAM or an analog module might not be observable, whereas the logic after these modules might not be controllable. Inserting scannable elements around these modules enhances the testability of your design.

refer: RC user guide(Design for Test in Encounter RTL Compiler) to more information on insertion of DFT shadow logic