What's One-Wait-State On-Chip ROM mean in TI?

[davyzhu]

Hello all,

I am reading TI's datasheet. And What's One-Wait-State On-Chip ROM mean? Can it be reprogrammable like Flash?

Any suggestions will be appreciated!
Best regards,
Davy

 

[Kral]

I don't know what specific device you're refering to, but in general, 1 wait state means that 1 machine cycle must elapse between the time the address (and any associated chip enable inputs) are stable and the time that data output will be valid.
Regards,
Kral

 

[davyzhu]

Hi Kral,

Thank you for your help
I mean the 320VC55x series(320VC5509).

Can I program the ROM or let TI do that? And if TI do that, how about the cost?

Any suggestions will be appreciated!

Best regards,
Davy

 

[puviarasu]

Hi TI doesn’t have flash or OTP ROM's, on their DSP’s what you are referring is the ROM which can be used for storing lookup tables and the other read only contents related to signal processing, that can be used for storing constants using compiler directives (in ROM memory range) and it will be loaded at the booting phase.

 

[Kral]

davyzhu,

The ROM must be factory programmed. However, the ROM address space can be mapped (via software) to external memory (EEPROM FLASH, etc). I don't know about the cost of factory programming for this device. However, it has been my experience on other devices that the break-even point cost-wise is 1000 devices. In other words, if you are using fewer than 1000 devices, you are better off, strictly from a cost perspective, using external memory. Of course, there are other considerations such as space, power, etc.
Regards,
Kral

 

[davyzhu]

Hi all,

I have one more question. If I have no on-chip Flash on TI's DSP, how to protect my code? For everyone can copy my code from Flash and produce another product?

All the best,
Davy

 

[puviarasu]

hi now i ghon through the DSP you r interested in they have given briefly about the ROM in the DSP in the Datasheet in 32nd page

"3.1.3 On-Chip Read-Only Memory (ROM)
The one-wait-state ROM is located at the byte address range FF0000h−FFFFFFh. The ROM is composed
of one block of 32K bytes and two 16K-byte blocks, for a total of 64K bytes of ROM. The ROM address space
can be mapped by software to the external memory or to the internal ROM. The 16K ROM blocks at FFC000
to FFFFFF can be configured as secure ROM. (See Section 3.1.4.)
NOTE: Customers can arrange to have the 5509 ROM programmed with contents unique to
any particular application. Contact your local Texas Instruments representative for more
information on custom ROM programming.
The standard 5509 device includes a bootloader program resident in the ROM. When the MPNMC bit field
of the ST3 status register is set through software, the on-chip ROM is disabled and not present in the memory
map, and byte address range FF0000h−FFFFFFh is directed to external memory space. A hardware reset
always clears the MPNMC bit, so it is not possible to disable the ROM at reset. However, the software reset
instruction does not affect the MPNMC bit. All three ROM blocks can be accessed by the program, data, or
DMA buses. The first 16-bit word access to ROM requires three cycles. Subsequent accesses require two
cycles per 16-bit word.
3.1.4 Secure ROM
Included in this 64K-byte ROM is a 16K-byte secure ROM (SROM) that is mapped into the memory space at
reset. This 16K-byte SROM is mapped out of the memory space by writing a “1” to the SROM disable bit field
of the Secure ROM Register (0x7C00) as shown in Figure 3−2. When the SROM disable bit is set, its setting
cannot be changed and the CPU or peripherals cannot access the on-chip SROM memory space. This ROM
block is not programmed on standard 5509 devices, but can be used to implement a custom, secure bootload
feature. Contact your local Texas Instruments representative for more information on custom ROM
programming."

you go through the data sheet briefly, if you want to work on it, that is the best idea.