elcielo
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What's New in Quartus II Software Version 4.0
Extending Altera's Software Technology Leadership
Version 4.0 of the Quartus® II software extends Altera's software technology leadership for high-density FPGA design and supports the new Stratix™ II FPGA family. The Quartus II software now features unique leadership advantages in:
Design flow methodology support
System design and intellectual property (IP) integration and IP evaluation
Place-and-route technology
Timing closure methodology
In-system verification technology
Stratix II devices are 50% faster than previous FPGA families and can reach even higher performance levels by taking advantage of the Quartus II software's advanced physical synthesis and timing closure methodologies. The Quartus II software technology leadership and the Stratix II device family deliver designers the highest performance and highest efficiency for high-density FPGA designs.
Extending Altera's Software Technology Leadership
The Quartus II software version 4.0 includes new technology to simplify and accelerate high-density FPGA design, including:
Memory Compiler Waveform Generation—Produces waveform displays of memory structure operation based on memory parameterization and configuration selections. This feature makes it easier to understand the effects of different memory configuration settings.
RTL Viewer—Provides a schematic representation of designs that can be used to analyze a design's structure before further behavioral simulation, synthesis, and place-and-route steps are performed. The RTL viewer allows designers to navigate a design's hierarchy and locate particular items of interest easily to aid in debugging and optimization. Selected items in the RTL viewer can be directly traced back to source design files.
Compilation Revisions—Allows designers to experiment using different compilation settings and assignments for a given design. A group of settings, assignments, and compilation results can be stored and processed separately as an individual design revision.
Physical Synthesis Support—Adds physical synthesis optimization support for the Stratix II FPGA family.
Design Space Explorer Distributed Computing Support—Design space explorer-automated design optimization script now supports distributed environments where multiple computers can run simultaneous compilations using different optimization settings.
SignalTap® II Advanced Triggering Feature—Provides a graphical environment to implement complex user-defined trigger logic to compare bus states and individual signals to initiate SignalTap II embedded logic analyzer data capture. This feature gives FPGA designers unprecedented flexibility to isolate system design problems in-system and at system speeds.
Faster Compile Times on Linux Platforms—Improves compile times by an average of 40%. Now supports Red Hat Linux versions 7.3 and 8.0.
What's New in Quartus II Software Version 4.0
Extending Altera's Software Technology Leadership
Version 4.0 of the Quartus® II software extends Altera's software technology leadership for high-density FPGA design and supports the new Stratix™ II FPGA family. The Quartus II software now features unique leadership advantages in:
Design flow methodology support
System design and intellectual property (IP) integration and IP evaluation
Place-and-route technology
Timing closure methodology
In-system verification technology
Stratix II devices are 50% faster than previous FPGA families and can reach even higher performance levels by taking advantage of the Quartus II software's advanced physical synthesis and timing closure methodologies. The Quartus II software technology leadership and the Stratix II device family deliver designers the highest performance and highest efficiency for high-density FPGA designs.
Extending Altera's Software Technology Leadership
The Quartus II software version 4.0 includes new technology to simplify and accelerate high-density FPGA design, including:
Memory Compiler Waveform Generation—Produces waveform displays of memory structure operation based on memory parameterization and configuration selections. This feature makes it easier to understand the effects of different memory configuration settings.
RTL Viewer—Provides a schematic representation of designs that can be used to analyze a design's structure before further behavioral simulation, synthesis, and place-and-route steps are performed. The RTL viewer allows designers to navigate a design's hierarchy and locate particular items of interest easily to aid in debugging and optimization. Selected items in the RTL viewer can be directly traced back to source design files.
Compilation Revisions—Allows designers to experiment using different compilation settings and assignments for a given design. A group of settings, assignments, and compilation results can be stored and processed separately as an individual design revision.
Physical Synthesis Support—Adds physical synthesis optimization support for the Stratix II FPGA family.
Design Space Explorer Distributed Computing Support—Design space explorer-automated design optimization script now supports distributed environments where multiple computers can run simultaneous compilations using different optimization settings.
SignalTap® II Advanced Triggering Feature—Provides a graphical environment to implement complex user-defined trigger logic to compare bus states and individual signals to initiate SignalTap II embedded logic analyzer data capture. This feature gives FPGA designers unprecedented flexibility to isolate system design problems in-system and at system speeds.
Faster Compile Times on Linux Platforms—Improves compile times by an average of 40%. Now supports Red Hat Linux versions 7.3 and 8.0.