What's a minimum size allowed for the Compiled Memories?

What's a minimum size allowed for the Compiled Memories? Let's say for the TSMC libraries...

How to choose when to use memories or flip-flops in the design? If I need to implement an array of 100, should I use a memory or flip-flops?

Thank you!

For your choice just synthesize your memories build with FFs and compare the size of a compiled ram. I know about a minimum ram size of 2 bit width and a depth of 32 at tsmc90

hbeck_ said:

For your choice just synthesize your memories build with FFs and compare the size of a compiled ram. I know about a minimum ram size of 2 bit width and a depth of 32 at tsmc90

Click to expand...

Thank you hbeck_!

As for the tsmc90 library, how is it possible to get its data sheet with cells and memories description? Is it free of charge?

What's about a BIST logic? Should it be generated separately or it comes "built-in" with such small memory?

Thank you!

Other point needs to be validate before choising FF or ram, a ram needs a BIST logic or software. So depending of your design, some time it is better to have only flipflop to reduce test time or reduce number of test mode. Also with FF we could have a reduced power consumption versus memory.
negative point, routability....

rca said:

Other point needs to be validate before choising FF or ram, a ram needs a BIST logic or software. So depending of your design, some time it is better to have only flipflop to reduce test time or reduce number of test mode. Also with FF we could have a reduced power consumption versus memory.
negative point, routability....

Click to expand...

rca,
Thank you fot your participation in the discussion!
you wrote: "with FF we could have a reduced power consumption versus memory". Would you explain please why? Each D-FF consist of at least two latches, each latch consist of at least two NOR gates, there is additional logic, with implement clock, set, reset, enable functionality while a Memory Cell has just two NOT buffers, which feed one another, plus some logic for the address line decoding. Both Memory and Flops works on the same clock. So, why Memory will consume more power? Could you explain please?
Thank you!

---------- Post added at 23:12 ---------- Previous post was at 22:47 ----------

And one more question: how SOFTWARE can replace BIST? Thank you!

---------- Post added at 23:52 ---------- Previous post was at 23:12 ----------

As for the Area point of view, what's the threshold?
With what amount of FFs/Cells the Area will be approximately equal?
What design takes usually more Area - with FFs or Memory?
Thank you!

When you have a core, you could read write a program to check the memory.
The threefold is your point of view.
In a project, i had the choice to add a ram but this one required a hardware BIST, a specific test mode or register to control this one, then I prefer to loose 10% of area but to simplify the implementation.
And I used ff without reset pin, without enable pin to select the minimum area ff.

who takes more power among ff's or m/m will basically depend on which type memory are you using and at what frequency levels. More frequency , more will be power consumption by memory . But AFAIK , FFs will consume more power , since it has resets and extra logic too.


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"More frequency , more will be power consumption by memory" - could you explain why? what's the frequency threshold?

So, do Memory or equivalent amount of FF cells take more power? Please assume both of them work from the same clock.

BTW, what memory will be more power consumed - synchronous or asynchronous?

Thank you!

Total power consumed is a combination of Power (static) + Power (dynamic) , where Power (dynamic) is proportional to frequency , so if u increase frequency , it will proportionally increase power .

About synchronous and asynchronous power consumption , AFAIK synchronous circuits will consume more power since you have a clock network , which takes maximum power in any design. Designing a asynchronous circuit , is itself a challenge.

rca,

You wrote: "I used ff without reset pin, without enable pin to select the minimum area ff" - How many FF without Reset and Enable pins smaller than fully functional DFF (with Reset, Set and Enable pins)?

Thank you!

---------- Post added at 22:09 ---------- Previous post was at 22:06 ----------

It seams that Reset Pin adds just one transistor to D-FF. How many does Enable pin add?

---------- Post added at 23:38 ---------- Previous post was at 22:09 ----------

A basic MUX2x1 implementation is by 6 CMOS (please correct me if I'm wrong). The D-FF implementation is by 11 CMOS (12 if with Reset).
So, Enable implementation for the D-FF "costs" 50% of it area - again, please correct me if I'm wrong.
Thank you!

---------- Post added at 23:41 ---------- Previous post was at 23:38 ----------

What's problem to implement a data array by Latches (1/2 of FF's area)?

Do Latches make problems during Scan Insertion?

Thank you!