what would happen for area and cell count, if we change frequency in synthesis?????

[vijayR15]

hai everyone,

In synthesis when i linearly changed the frequency from 100mhz to 500mhz i cant understand why the number of cells and area are increasing and decreasing???? please let me know if anyone knows...


Thanks in advance.....:smile:

 

[eld03]

The synthesis tool inserts logic cell to meet the timing and reduce slag/skew. doing so it may have to add more cell to balance load, so again some cells are added. therefore the cells increase. High performance cells are handcrafted at schematic level and layout made by direct silicon layout compilation.
Sorry but bluntly i have to say synthesis tools are for those tech guys who don't know to design a bit complex circuits by first principals , but know how to manage the functionality, they are MBA( verilog/vhdl) in circuit design!

 

[vijayR15]

Thanks buddy its more helpfull to me...

hai eldo3,

When I worked with the 100mhz frequency the area is 16699. When i go for 200mhz its increasing to 16730. Actually what is happening in area wise when i goes on increase with frequency.

 

[yadavvlsi]

Increasing the frequency means you are decreasing time period. So you will faster gate to meet timing. Faster gates have MOSFET having wider channel. Hence larger area. If you further increase frequency you will see a considerable increase in area.

 

[tariq786]

hi Yadavvlsi,

Could you throw more light on the effect of wider channel? My understanding is that transistors are getting tiny and tiny and how does this tie with widening of channel? Please explain more in terms of npn theory

 

[yadavvlsi]

Tariq, Wider channel is related to MOS not BJT. With the help of scaling we are reducing transistor dimensions (channel length and width). So we are getting faster and faster gates. But in VLSI interconnect delay are very high due resistance and capacitance they offers. So interconnects contribute a large RC delay. To achieve high frequency we need minimize the RC delay of interconnects and to reduce RC delay we requires a high drive strength gates (standard cells). Drive strength is related to current which is directly proportional to transistor width.
https://www.edaboard.com/threads/230661/#post995283
MOSFET - Wikipedia, the free encyclopedia

 

[tariq786]

Hey Yadavvlsi,
Thanks a lot. I was also talking about FET and not bjts. Your explanation makes perfect sense. Any idea what those standard cells might be? I have a standard cell library, how can i search for these wide area cells?

very nice.

 

[yadavvlsi]

In standard cell library you will find same gate with different drive strengths. Suppose for a buffer you will find BUFFD1, BUFFD2, BUFFD4. The number 1,2,4 represents the drive strength of buffer. Naming convention for different libraries is different. In timing library you will find the area and timing information. But if you wants to see width of transistor used in a cell. You need open spice file of that library.

 

[vijayR15]

hai yadavvlsi and tariq,

your queries and answers sounds good.... Tariq as yadavvlsi said you can get each individual cell area infromation in .lib file or else you can also get it through cell information .lef file there is a option "sizeby" through that you can find the wide area cells.. mostly the cells with high drive strength will have wide area... :razz:

 

[eld03]

Smaller area device will be fast , but is it lacks drive. there is a optimal point were drive and area meet the basic requirement. designer adjust for higher width to get drive at the cost of power.
the best way to get min devices for synthesis is
1. Use Synopysis tools.
2. Use gates with lower number of inputs , debar the device that have more inputs.
3. identify the device that have poor drive and more input load ; avoid them or lower their priority during synthesis
4. avoid using functional code for synthesis , try to use gate level code if possible
5. During lowing of time in order to keep slack difference in control , adjust the drive the synthesis inserts cells.
hope its OK

 

[yadavvlsi]

Smaller area device will be fast

You listed very good points to obtain good synthesis result. But Can you elaborate how device with smaller area will be faster.?