What will happen if I declare wire and port with same name in verilog ?
Please refer to below example for question (clk1 is declared as port and wire )
always @ (posedge clk1 or negedge rstn1)
begin
if(~rstn1)
begin
counter <= 5'd30;
end
else
begin
if (counter == 5'd0)
begin
counter <= 5'd30;
end
else
begin
counter <= counter - 2'd2;
end
Verilog implicitly connects a port to a signal with the same name. If you don't declare the signal, Verilog implicitly creates a wire for you with the same name as the port, as is the case with rstn1 and out1.
I highly recommend using the Verilog-2001 way of declaring ports and signals together so that each name only appears once.