What value should I set on wire_load in .18 process(tsmc) ?

[cloudsuns]

wire_load

Hi ,everyone
what value should I set on wire_load in .18 process(tsmc)

 

[melonpy]

Re: wire_load

Can you give me more detail description about your question?

 

[ic_design]

The wire_load must be set based on the size (gates in design)of chip and the library.

 

[zyphor]

Re: wire_load

why not try physical compiler to avoid this arguelessness question?

 

[petloid]

Re: wire_load

A good rule of thumb is for the estimated wirecap per fanout to be the same as the input gate cap of the largest inverter using a single P and N transistor. If you've got lots of gates, or are simply cautious, you can increase this value by say 50%.
-Graham

 

[linuxluo]

Re: wire_load

hi,
dont try to estimate the wireload under 0.18um , using pc

 

[zyphor]

Re: wire_load

I agree, below .18 real environment should be considered for delay calculation. If you still use DC, your convergence cycle will be enlarged, and many many useless buffer, inverter will be introduced.

 

[cnspy]

Then which kind of eda tools should be used in < .18 design?

 

[zyphor]

Re: wire_load

Phsical compiler