What to determine the process technology options?

Hi, guys,

I need to measure a 1us~10us current pulse. The design goal of the bandwidth is 1MHz. I have two options about process technology: ON semiconductor C5 CMOS 0.5um and IBM 7RF CMOS 0.18um. Anyone has any experience about that? Or, can anyone give suggestion about how to choose the process technology regarding my aimed application?

Your decision should depend on a lot more than just a bandwidth condition, I think. A not-too-complex 1MHz bandwidth system should well be feasible in a 0.5µm CMOS process - and this rather old C5 2- or 3-layer process probably is much cheaper than a 7-layer RF 0.18µm CMOS process.

Think of more categories: operating voltages (C5 has HV transistors), routing complexity needed (no. of layers), planned volume (chip cost), process life cycle, ...

erikl said:

Your decision should depend on a lot more than just a bandwidth condition, I think. A not-too-complex 1MHz bandwidth system should well be feasible in a 0.5µm CMOS process - and this rather old C5 2- or 3-layer process probably is much cheaper than a 7-layer RF 0.18µm CMOS process.

Think of more categories: operating voltages (C5 has HV transistors), routing complexity needed (no. of layers), planned volume (chip cost), process life cycle, ...

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The cost is not an issue to me. The voltage supply is not a problem.

I was concerned about speed. You said that 1MHz bandwidth is applicable with 0.5um process. I guess you meant 1MHz bandwidth is achievable by a single stage OTA.

Noise maybe a issue. I need to measure a pA level current pulse with 10us pulse width. Any further suggestion about that?

P.S. I do not know how to edit my original message to put new information in. I had to put this information in my reply message here.

hyleeinhit said:

I was concerned about speed. You said that 1MHz bandwidth is applicable with 0.5um process. I guess you meant 1MHz bandwidth is achievable by a single stage OTA.

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I said for a not-too-complex system; a 1 MHz bandwidth should also be feasible for a 2- or 3-stage OTA in a 0.5µm process, but certainly needs a larger operation current for that than a same-bandwidth amp in 0.18µm.

hyleeinhit said:

Noise maybe a issue. I need to measure a pA level current pulse with 10us pulse width. Any further suggestion about that?

Click to expand...

Generally, for comparable operation currents, noise tends to be a bit less in lower process sizes (as long as no gate current noise is contributing, but this shouldn't yet be a problem for 0.18µm technologies with tox=4nm).
However: s. above!

hyleeinhit said:

P.S. I do not know how to edit my original message to put new information in.

Click to expand...

AFAIK this is only possible within one hour after the original post.

erikl said:

I said for a not-too-complex system; a 1 MHz bandwidth should also be feasible for a 2- or 3-stage OTA in a 0.5µm process, but certainly needs a larger operation current for that than a same-bandwidth amp in 0.18µm.


Generally, for comparable operation currents, noise tends to be a bit less in lower process sizes (as long as no gate current noise is contributing, but this shouldn't yet be a problem for 0.18µm technologies with tox=4nm).
However: s. above!


AFAIK this is only possible within one hour after the original post.

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Thanks for your reply.

I don't quite understand your saying: a 1 MHz bandwidth in 0.5µm process, certainly needs a larger operation current for that than a same-bandwidth amp in 0.18µm.

We know that about GBW (Gain–bandwidth product): GBW=gm/CL and gm=2*Id/(Vgs-Vth)
For the two process tech, if the bias current , (Vgs-Vth) and CL are equal, GBW is equal.

erikl said:

Generally, for comparable operation currents, noise tends to be a bit less in lower process sizes (as long as no gate current noise is contributing, but this shouldn't yet be a problem for 0.18µm technologies with tox=4nm).
However: s. above!.

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I want to figure out why this is true. The noise includes thermal noise and 1/f noise.

The thermal noise is: In^2=4kTγ*gm, where gm=2*Id/(Vgs-Vth).
For these two process technologies, if Id and (Vgs-Vth) are equal, the thermal noise is equal. Am I right?

The 1/f noise is: Vn^2=K/(CoxWLf).
0.18um process has larger Cox than 0.5um process. If assuming K's change is small for these two process tech, and W, L are the same, 0.18um process thereby has lower 1/f noise than -.5um. Am I right?

hyleeinhit said:

I don't quite understand your saying: a 1 MHz bandwidth in 0.5µm process, certainly needs a larger operation current for that than a same-bandwidth amp in 0.18µm.

We know that about GBW (Gain–bandwidth product): GBW=gm/CL and gm=2*Id/(Vgs-Vth)
For the two process tech, if the bias current , (Vgs-Vth) and CL are equal, GBW is equal.

Click to expand...

This equation results in a rough first-order estimation of the GBW, but it considers just the most dominant pole. As you may know, an OTA additionally has some less dominant poles, which co-determine the actual bandwidth. Also, larger process sizes usually have larger (input and output) built-in capacitances at their active devices (Cgs, Cgd, Cdb), hence need larger operating currents for comparable time constants. And not to speak of usually larger parasitic caps from routing connections.

Moreover, OTAs usually need frequency compensation. By using pole splitting, the OTA's output may not stay the most dominant pole, so renders the above equation invalid.

hyleeinhit said:

The thermal noise is: In^2=4kTγ*gm, where gm=2*Id/(Vgs-Vth).
For these two process technologies, if Id and (Vgs-Vth) are equal, the thermal noise is equal. Am I right?

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In a first-order approximation, yes. But there are more noise sources than drain noise current, also thermal ones. Usually contribute less at lower process nodes.

And I still think you need less current for same GBW at lower nodes, s. above.

hyleeinhit said:

The 1/f noise is: Vn^2=K/(CoxWLf).
0.18um process has larger Cox than 0.5um process. If assuming K's change is small for these two process tech, and W, L are the same, 0.18um process thereby has lower 1/f noise than -.5um. Am I right?

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If you really keep W & L the same, absolutely. Also fits with values from literature.

You say you want to measure a pulse, but what about it
are you trying to measure? That affects approach and
foundry vehicle.

a 1MHz BW system would on its face seem inappropriate
to measuring anything about a 1uS pulse - not its width,
not its amplitude (unless you like 3dB worth of error),
certainly not rise / fall edge attributes.

I'd expect C5 to support 200MHz-ish FF toggle rates
(maybe needing well crafted logic to do anything useful
at this rate). At 100MHz you could get pulse width timing
at 1% accuracy, a decent peak detector ought to be
able to follow at some lesser accuracy and get you an
amplitude voltage you can digitize (maybe wanting a
cal-map to deal with fixed errors) at a more leisurely
pace (you can find many papers on C5 based ADCs).

So what is it that you really want to accomplish?

erikl said:

In a first-order approximation, yes. But there are more noise sources than drain noise current, also thermal ones. Usually contribute less at lower process nodes..

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I still do not quite understand this point. Can you give an example? Thanks.

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dick_freebird said:

You say you want to measure a pulse, but what about it
are you trying to measure? That affects approach and
foundry vehicle.

a 1MHz BW system would on its face seem inappropriate
to measuring anything about a 1uS pulse - not its width,
not its amplitude (unless you like 3dB worth of error),
certainly not rise / fall edge attributes.

I'd expect C5 to support 200MHz-ish FF toggle rates
(maybe needing well crafted logic to do anything useful
at this rate). At 100MHz you could get pulse width timing
at 1% accuracy, a decent peak detector ought to be
able to follow at some lesser accuracy and get you an
amplitude voltage you can digitize (maybe wanting a
cal-map to deal with fixed errors) at a more leisurely
pace (you can find many papers on C5 based ADCs).

So what is it that you really want to accomplish?

Click to expand...

Thanks for the information. I want to measure a 10us pulse width current. Forgot to mention in the original post: the pulse width is ~pA. The time between two pulses is unknown.

Please refer to the attachment for the waveform.

Pulse width or PW50[%] and Tr [10~90%] rise time are two different attributes.

The lithography aperture size and capacitance will affect the rise time for a given source impedance. The actual source impedance is limited to the area of the junction that determines RdsOn.


To measure slew rate, one needs a DSO with approx 300MHz for 1ns rise time which you can scale to your requirements.

I'd have to say "good luck" at measuring a 1pA pulse -
even picoammeters for DC are specialty gear. I'd guess
a transimpedance amp is wanted at the front end before
anything else. You might look at what image sensor
(slow, sensitive) and fiber optic (fast, not so sensitive)
receiver front ends have to teach.

erikl said:

In a first-order approximation, yes. But there are more noise sources than drain noise current, also thermal ones. Usually contribute less at lower process nodes..

Click to expand...

hyleeinhit said:

I still do not quite understand this point. Can you give an example?

Click to expand...

Apart from drain-referred noise current, also gate-referred noise voltage contributes to total thermal noise (to flicker noise, too).

Noise models can be rather complex and depend on operation regions and modes. Too much to explain within this frame. I'd suggest to check the appropriate literature, e.g. in Binkley's book TRADEOFFS AND OPTIMIZATION IN ANALOG CMOS DESIGN, chap. 3.10 NOISE. Here's the 1^st page of this chapter: View attachment Binkley__noise_p188.pdf.

erikl said:

Apart from drain-referred noise current, also gate-referred noise voltage contributes to total thermal noise (to flicker noise, too).

Noise models can be rather complex and depend on operation regions and modes. Too much to explain within this frame. I'd suggest to check the appropriate literature, e.g. in Binkley's book TRADEOFFS AND OPTIMIZATION IN ANALOG CMOS DESIGN, chap. 3.10 NOISE. Here's the 1^st page of this chapter: View attachment 111321.

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Thanks so much. I would check it out.

dick_freebird said:

I'd have to say "good luck" at measuring a 1pA pulse -
even picoammeters for DC are specialty gear. I'd guess
a transimpedance amp is wanted at the front end before
anything else. You might look at what image sensor
(slow, sensitive) and fiber optic (fast, not so sensitive)
receiver front ends have to teach.

Click to expand...

Thanks for your reply.

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dick_freebird said:

I'd have to say "good luck" at measuring a 1pA pulse -
even picoammeters for DC are specialty gear. I'd guess
a transimpedance amp is wanted at the front end before
anything else. You might look at what image sensor
(slow, sensitive) and fiber optic (fast, not so sensitive)
receiver front ends have to teach.

Click to expand...

Thank you.