what this error means....?plz....

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Sasi Cm

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assign b[0:4]=a[0:4];
for this line i get this folloeing error.
# ERROR: compare.v(12): LHS in force may not be a net: b
 

Without seeing the rest of yuor code, it looks like you have not defined b before assigning to it.

r.b.
 

Code: 
module compare(a,b,out0,out1,out2,temp,temp1,temp2);
input [0:19]a;
output [0:4]b;
//reg [0:4]b;
output [0:1]out0,out1,out2;
reg [0:1]out0,out1,out2;
output [0:4] temp,temp1,temp2;
reg [0:4] temp,temp1,temp2;
always @(a)
begin
assign b[0:4]=a[0:4];
assign temp=b[0:4]^a[5:9];
if(temp[0]!=1&&temp[1]!=1&&temp[2]!=1&&temp[3]!=1&&temp[4]!=1)
begin
out0<=0;
end
else if(temp[0]!=0&&temp[1]!=0&&temp[2]!=0&&temp[3]!=0&&temp[4]!=0)
begin
out0<=10;
b[0:4]<=~a[0:4];
end
else
begin
out0<=11;
b[0:4]<=temp[0:4];
end

assign temp1=a[0:4]^a[10:14];
if(temp1[0]!=1&&temp1[1]!=1&&temp1[2]!=1&&temp1[3]!=1&&temp1[4]!=1)
begin
out1<=0;
end
else if(temp1[0]!=0&&temp1[1]!=0&&temp1[2]!=0&&temp1[3]!=0&&temp1[4]!=0)
begin
out1<=10;
b[0:4]<=~b[0:4];
end
else
begin
out1<=11;
b[0:4]<=temp1[0:4];
end

assign temp2=a[0:4]^a[15:19];
if(temp2[0]!=1&&temp2[1]!=1&&temp2[2]!=1&&temp2[3]!=1&&temp2[4]!=1)
begin
out2<=0;
end
else if(temp2[0]!=0&&temp2[1]!=0&&temp2[2]!=0&&temp2[3]!=0&&temp2[4]!=0)
begin
out2<=10;
b[0:4]<=~b[0:4];
end
else
begin
out2<=11;
b[0:4]<=temp2[0:4];
end

end
endmodule

This is the coding and i declared b also....but i don't know why the error came....
 

As far as I remember all the outputs shoud be defined as registers and inputs as wire. I see that you have commented the //reg [0:4]b; statement
 

Hi

You have secveral isues in this code. In addition to the other ones pointed out:

* you are using assign with "b" but you had planned to define it as a register. You can't assign to a register.
* Verilog sensitivity lists are no longer required and have not been for quite some time. If you do use them , you must make them complete. Where you type "always @ (a)" you must also include temp.

* And here - " b[0:4]<=~b[0:4];" - you have a problem. This sort of operation requires a storage of state, which means a flip-flop, which means synchronous logic, which means you need to introduce a clock. I believe someone else pointed this out in a previous thread. Without a FF, you would just feed a NOT gate's output back to its input which creates an oscillator dependent on process, temperature and voltage, which I am sure you don't want. And I'm not entirely sure this would infer that anyway. Either way, I don't think you will get what you think you want.


r.b.
 
Last edited:

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