what the maxim of the skew between the P and N line of a differential signal?

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daraemon_liu

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Hi eveyone,
In my recent project,I try to lay a pair of differential output signal in the PCB.
the frequency of the signal is 5.6Ghz, my question is what the maxim of the skew should I control between the P line and N line in the PCB? How can I calculate the skew?
TKS
 

High speed differential interfaces, e.g. PCIe or SATA have specific requirements for differential skew, you have to refer to the standards. In a rough estimation, you can convert the length difference to skew, using the known PCB propagation speed.
 

Thank you for your reply.
But I think what you say is how to calculate the skew between several differential outputs of an certain interface,for example ,in the SFI-4 interface ,you can get the definite skew tolerance value between the clk and the data refering to the SFI-4 standard.
I just want to a common differential output,which certainly have 2 singal line P and N,what the maixmum skew between these two line? What will happen in the signal if there is a excessive skew?
 

Skew converts to common mode signal. The main reason, why some interface standards set restrictive skew limits is EMI related. They want to avoid common mode waves, because they cause radiated interferences. The common mode tolerance of usual differential receivers would be good enough to tolerate much more differential skew. At worst case, the jitter is increased. So the question, how much skew is acceptable, goes back to you.
 

Check this IEEE paper if you can :"Computation of Intra-pair Skew for Imbalance Differential Line using Modified Mixed-mode S-parameter"
 

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