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what the DFT rule mean???

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xiongdh

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R 10.4.6 Do not allow LSSD latch stages to receive inputs in either the data path or scan path from a Mux-D Flip-Flop in the same phase
Certification requirement: ATPG DRC clean.
R 10.4.7 Do not allow Mux-D Flip-Flops to receive inputs in either the data path or scan path from a LSSD latch in the same phase
Certification requirement: ATPG DRC clean.

can some one explain why???
 

If latch and flip-flop in the same block and scan is inserted for DFT. Can the two elements be in the same chain?
 

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