what prevent the top metal layer for power to become a plane?

Hello,

Typically the top two metal layers are used for power distribution network, they are thicker, wider compared to other metal layers because low resistance is required in the power distribution network. And as I know, they can also be built as a power plane, not a net-like PDN. It seems that the power plane should be better than the traditional PDN because it offers lower resistance. If so, why not build all the IC with power plane rather power network? What makes a net-like PDN still survive? Plz share you idea.:roll::roll::roll:

I think you are looking top metal layers just as a power network. But signals coming into the chip have to come through package, into the logic gates so in some ways it has to travel from the top to logic gates which is in Metal1 or Metal2. For example the clock signal coming into the chip will have to power the flops so they have to routed into the design. A portion of the top level metals are used for top level signal routing. This is where the trade off comes depending up number of signals, their frequencies and power grid have to adjust as to how they will be routed. these factors make power network a net rather then the plane. The situation becomes worse when the number of power networks have more than one Vdds.

I agree with you. I read some paper which talks something the pad on the die. It's said that the pitch of the pads on the die is somewhat >30 um, which is much higher than that of the pitch of the power network. Is the routability still an issue under this case. I am just interested. Please share your opinion. For some chips, they have multi Vdds from off-chip. This is what you mean, right? And they also consume some space to build their own PDN, right? Thanks.

artmalik said:

I think you are looking top metal layers just as a power network. But signals coming into the chip have to come through package, into the logic gates so in some ways it has to travel from the top to logic gates which is in Metal1 or Metal2. For example the clock signal coming into the chip will have to power the flops so they have to routed into the design. A portion of the top level metals are used for top level signal routing. This is where the trade off comes depending up number of signals, their frequencies and power grid have to adjust as to how they will be routed. these factors make power network a net rather then the plane. The situation becomes worse when the number of power networks have more than one Vdds.

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I agree with you. I read some paper which talks something the pad on the die. It's said that the pitch of the pads on the die is somewhat >30 um, which is much higher than that of the pitch of the power network. Is the routability still an issue under this case. I am just interested. Please share your opinion. For some chips, they have multi Vdds from off-chip. This is what you mean, right? And they also consume some space to build their own PDN, right? Thanks.

artmalik said:

I think you are looking top metal layers just as a power network. But signals coming into the chip have to come through package, into the logic gates so in some ways it has to travel from the top to logic gates which is in Metal1 or Metal2. For example the clock signal coming into the chip will have to power the flops so they have to routed into the design. A portion of the top level metals are used for top level signal routing. This is where the trade off comes depending up number of signals, their frequencies and power grid have to adjust as to how they will be routed. these factors make power network a net rather then the plane. The situation becomes worse when the number of power networks have more than one Vdds.

Click to expand...