What may be the cause of PLL peaking?

[liberal]

I design a pll,but there is a peaking at Fbw when roll-off.i want to konw what cause it?how to solve it?and good papers about it?

 

[biff44]

pll peaking versus phase margin]

PLL operates pretty much like a classical control loop.

The closed loop gain of a loop with a forward gain of G(s) and a feedback gain of H(s) is

Gain = G(s)/(1+GH(s))

GH(s) is the gain when the feedback loop is "opened up", or commonly known as the "open loop gain".

So, the closed loop gain behaves well EXCEPT when it goes to infinity. It can go to infinity whenever the quantity GH(S)= -1. In this case, the closed loop gain is
Gain = G(S)/(1-1) = infinity, or the loop oscillates.

So lets say instead that GH(S) = -.98

The closed loop gain does not go to infinity, but gets really high! So any perturbation to the loop has an exagerated response (ringing in the time domain, or peaking in the frequency domain).

So, a good control loop engineer designs his control loop filter to not exhibit this abnormal high gain condition. He realizes that there are two criteria he has to simultaneously meet:
1) When the magnitude of GH(s) is around 1 (or 0 dB), then the open loop phase angle of GH(s) had better be far away from 180 degrees. This is known as phase margin.

2) When the phase angle of GH(s) is around 180 degrees, then the open loop gain had better be far away from 0 dB. This is called gain margin.

It is often helpful to plot the open loop gain and phase angle on a "Bode plot" to visualize this.

IF the above two criteria are not met, then the control engineer adjusts the loop parameters accordingly to do a better job. When he achieves 60 degrees of phase margin, he notes that the "peaking" has completely gone away.

He "adjusts" the loop parameters by changing the gain, dominant pole frequency, or dominant zero frequency.

So, in summary, you get peaking because in your control loop filter, you are making the system "divide by zero" at some frequency near your control loop bandwidth.

Fixing the ringing is not that intuitively obvious. In a standard type of pll, where there is an integrating op amp in the loop filter, there input resistor R1 connected to the inverting input, and the op amp output is fed back to the inverting input via a series RC pair, R2 and C. Then the product R1 and C determine the pole frequency and "gain" (gain is a function of frequency). The product R2 and C determine the zero frequency. In a crude way, one can then vary the R2 value around to try to move the zero frequency closer but always above to the pole frequency, which gives more phase margin and less ringing.

 

[liberal]

pll peaking

thank you!
and does the loop bandwidth infulencce it ?i remember when i decrease the loop bandwidth ,the peaking is bigger.and when i use a amp in the loop,even though the margin is big enough ,the peaking is big.
and how much the peaking is means better?

 

[biff44]

pll peaking is

Yes, excess peaking is bad.

I suggest you get onto some sort of control loop program and learn about poles and zeros.

The loop bandwidth has nothing to do with stability, except at very high (>10 MHz) loop bandwidths where component parasitics add extra poles.

You can have a 1 Hz loop bandwidth that is an unstable system, and a 5 MHz loop bandwidth that is completely stable.

 

[liberal]

pll reference clock frequency site:edaboard.com

ok,thank you!
and i have another question.when i measure my pll phase noise, about 6-10db degration as simulated by adiSIMpll,what may cause it ?

 

[biff44]

why peaking in pll

Almost anything. Are you measuring double sided but simulating single sided.

Is your power supply noiseless. Did you simulate the input noise voltage at the op amp input. Is the VCO bypassed with a bank of caps, perhaps as big as 47 uF. Do you have enough gain in the loop filter to reduce the vco free running noise down to the expected locked voltage. etc etc.

 

[liberal]

Re: PLL peaking

i measure the phase noise with agilent E5052,and simulate it with ADIsimpll.
maybe all single sided?
and i have read an articel on microwave journal October 2006 Issue
A Practical Design of a Low Phase Noise Airborne X-band Frequency Synthesizer
**broken link removed**

for equation 16 ,it cal the phase noise +20logN and add 6dB,i dont konw how cause 6dB?and for equation 20 a fractional pll, it add 12dB?why?

 

[hackjiang]

Re: PLL peaking

Yes, excess peaking is bad.

......
The loop bandwidth has nothing to do with stability, except at very high (>10 MHz) loop bandwidths where component parasitics add extra poles.

.........

I don't think so. Basically with the fixed loop zero bandwidth is proportional to the phase margin.
Regards.

 

[biff44]

Re: PLL peaking

???

 

[eternal_nan]

PLL peaking

Not sure what hackjiang is trying to say, but I also have a comment on the: "loop BW has nothing to do with stabilty", in general it is not true. For charge pump PLLs with digital phase detectors loop BW needs to be at least 10 times less than the lowest PLL reference clock frequency or the loop starts going unstable, this is due to the fact that this type of PLL is really a sampled system and the BW of the loop is getting to be too close to sampling freq. to guarantee proper operation.

 

[biff44]

Re: PLL peaking

Good point. BUT, I think it is not the fact that it is a digital phase detector. It usually is the fact that there is a digital time delay in the divider chain causing an eΛ-j τ phase sift in the control loop that screws you up. So, if you have a divide by N=20,000, you have to wait for 20,000 cycles of the VCO frequency before you can observe the phase.

You are very right, though, in that if you have a slow sample frequency and it resides inside of the loop bandwidth, you will see huge reference spurs in the RF output.

 

[hackjiang]

Re: PLL peaking

???

Sorry, I didn't made it clear.
When we design a charge pump pll with PFD used, loop bw should be chosen first.
The zero frequency in passive filter should be well simulated to get the max phase margin of the loop.
Wbw/Wz is proportional to the phase margin. It's the simple design principle.
Regards.

 

[liberal]

Re: PLL peaking

we choose a loop bandwidth at the point where the free-VCO phase noise equal to the reference phase noise .if the bandwidth lower than that point the peak will big.right?
and can anyone help me about the artice in microwave journal?