what is wrong with this PLL loop filter?

[eejli]

pll loop filter

Dear Folks,

I am testing my PFD, charge pump and loop filter. They are connected in series.

As shown in the attached figure, the loop filter voltage drop down after the increasing ramp when "UP" signal =1. Where does this voltage drop come from. I am using ideal resistor and even the ideal charge pump (veriloga model).

I guess it is from the loop filter time constant. I am using a big cap, 72 uF. How can I avoid this big voltage drop since I found it cause problem for my PLL locking? In the lock process the loop voltage cannot increase at all after several micro second's settling.

Thanks!

 

[oermens]

loop filter

just a side remark... 72uF? I hope you don't plan on implementing this on chip...

 

[saro_k_82]

pll loop filter program

You loop filter parameters dont seem to be right. How did you arrive at these values

 

[ravirajdv]

loop filter parameters

Hi eejli,
Few observations;
1> The first cap seems too huge. Having a 72uF cap in parallel with 39pF will have no effect, meaning the 39pF cap becomes useless so also the 80 pF.
2> As a thumb rule, the cap C2 ( the 39pF) should be nearly 1/10 of the C1 ( the 72uF). As I understand this cap is put to add additional pole to improve the PM, So it would be better put at the end, after the 2 stage filter.

As saro_k_82 suggested, just check the loop parameters.
Regards,
RDV

 

[eejli]

loop filter charge pump

Thank you guys,

The 72 uF is off chip on the board. This big cap value comes from the big vco gain Kvco_max=2.5GHz/V, charge pump current is 200 uA and divider ratio=200.

I hope the loop bandwidth is about 500khz. I plug in this numbers in a ADS program, and it comes out the loop filter values with phase margin=50 degree and reference spur attenuation > 70dB.

 

[saro_k_82]

how to understand the loop filter in the pll

The calculations are obviously wrong. The zero frequency (1.25K and 72uF) comes to less than 2Hz!!.. the second pole (by normal PLL TF conventions) is at 3MHz (which makes the optimal BW at around 2KHz) and the third pole is at 2MHz!!