kvnsmnsn
Junior Member level 1
Perhaps on a whim, I decided to code my Verilog module (sPivots) with all my inversions done by a (Nt) module, Nands done by a (Nd2) module, Nors done by a (Nr2) module, and inverted multiplexers done by a (Nmx2) module, all of which I wrote myself. Then I wrote my Verilog and wrote module (t23_sPivots) to test it. Since then I created module (t23_sPivots_Bug) to capture the behavior I don't understand. There's a line early on in (sPivots) that calls (Nt) on (loadingUp) and returns the inverted value of it in (loadingDown). As you can see, when the value of (loadingUp) is (0), the value of (loadingDown) is (x). Why is that? Why isn't my (Nt) module working right to assign (loadingDown) to (1)? My line simply says: "Nt aT( loadingDown, loadingUp);". If I replace that with "assign loadingUp = ~ loadingDown;", it works just fine; (loadingDown) gets the value (1) just as you'd expect. Why isn't my (Nt) module doing the same thing?
My module (sPivots) is:
My module (t23_sPivots_Bug) is:
My style is to properly indent the code I want to keep, but when I do my debugging to find out why I'm getting unexpected behavior, I add code that I don't indent. I ran this on "www.edaplayground.com" and got these results:
I can't figure out why my (Nt) module isn't working. Any feedback on this would be greatly appreciated.
My module (sPivots) is:
Code:
// (c) Kevin Simonson 2025
module Nt ( output rslt
, input op);
supply0 ground;
supply1 power;
nmos n( rslt, ground, op);
pmos p( rslt, power , op);
endmodule
module Nd2 ( output rslt
, input aOp
, bOp);
supply0 ground;
supply1 power;
wire srCn;
nmos na( srCn, ground, aOp);
nmos nb( rslt, srCn , bOp);
pmos pa( rslt, power , aOp);
pmos pb( rslt, power , bOp);
endmodule
module Nr2 ( output rslt
, input aOp
, bOp);
supply0 ground;
supply1 power;
wire srCn;
nmos na( rslt, ground, aOp);
nmos nb( rslt, ground, bOp);
pmos pa( srCn, power , aOp);
pmos pb( rslt, srCn , bOp);
endmodule
module Nmx2 ( output rslt
, input pLow
, pHgh
, dLow
, dHgh);
wire mux;
nmos nl( mux , dLow, pLow);
pmos pl( mux , dLow, pHgh);
nmos nh( mux , dHgh, pHgh);
pmos ph( mux , dHgh, pLow);
Nt t( rslt, mux);
endmodule
module MuOuNmx #( nmBits = 2
, localparam maxBit = nmBits - 1)
( output [ maxBit:0] rslt
, input pHgh
, pLow
, [ maxBit:0] dHgh
, [ maxBit:0] dLow);
genvar bt;
generate
for (bt = 0; bt < nmBits; bt = bt + 1)
begin
Nmx2 m( rslt[ bt], pHgh, pLow, dHgh[ bt], dLow[ bt]);
end
endgenerate
endmodule
module LessThan #( kyBits = 2
, localparam keyHigh = kyBits - 1)
( output rslt
, input [ keyHigh:0] lssr
, [ keyHigh:0] grtr);
assign rslt = lssr < grtr;
endmodule
module sPivots #( kyBits = 2
, nmQueues = 6
, localparam keyHigh = kyBits - 1)
( output chsLf
, chsMd
, chsRg
, d_loadingDown
, input loadingUp
, [ keyHigh:0] hdUl
, [ keyHigh:0] hdUm
, [ keyHigh:0] hdUr
, [ keyHigh:0] hdDl
, [ keyHigh:0] hdDm
, [ keyHigh:0] hdDr);
wire lfLtMd, lfLtRg, mdLtRg;
wire [ keyHigh:0] ntHdLf, ntHdMd, ntHdRg;
wire loadingDown;
wire ntChsLf;
wire mdGeRg;
wire lfGeMd;
wire lfGeRg;
Nt aT( loadingDown, loadingUp);
Nt bT( mdGeRg, mdLtRg);
assign d_loadingDown = loadingDown;
generate
if (4 < nmQueues)
begin
MuOuNmx #( kyBits) lMu( ntHdLf, loadingUp, loadingDown, hdDl, hdUl);
MuOuNmx #( kyBits) mMu( ntHdMd, loadingUp, loadingDown, hdDm, hdUm);
LessThan #( kyBits) lmL( lfLtMd, ntHdMd, ntHdLf);
LessThan #( kyBits) lrL( lfLtRg, ntHdRg, ntHdLf);
Nd2 cD( ntChsLf, lfLtMd, lfLtRg);
Nt dT( chsLf, ntChsLf);
Nr2 eR( chsMd, lfLtMd, mdGeRg);
Nr2 fR( chsRg, lfLtRg, mdLtRg);
end
else
begin
assign chsLf = 1'b0;
Nr2 nR( chsMd, loadingUp, mdGeRg);
Nd2 oD( chsRg, loadingDown, mdLtRg);
end
endgenerate
MuOuNmx #( kyBits) rMu( ntHdRg, loadingUp, loadingDown, hdDr, hdUr);
LessThan #( kyBits) mrL( mdLtRg, ntHdRg, ntHdMd);
endmodule
Code:
// (c) Kevin Simonson 2025
module t23_sPivots_Bug;
reg ldngUp;
reg [ 1:0] hdUl;
reg [ 1:0] hdUm;
reg [ 1:0] hdUr;
reg [ 1:0] hdDl;
reg [ 1:0] hdDm;
reg [ 1:0] hdDr;
wire chsLf;
wire chsMd;
wire chsRg;
wire d_loadingDown;
sPivots #( 2, 3)
p( chsLf, chsMd, chsRg
, d_loadingDown
, ldngUp, hdUl, hdUm, hdUr, hdDl, hdDm, hdDr);
initial
begin
ldngUp = 1'b0;
hdUl = 2'b00; hdUm = 2'b10; hdUr = 2'b10;
hdDl = 2'b00; hdDm = 2'b00; hdDr = 2'b00;
#3 $finish;
end
always @( ldngUp, hdUl, hdUm, hdUr, hdDl, hdDm, hdDr, chsLf, chsMd, chsRg)
begin
$display
( "t: %2t, lu: %1b, ul: %2b, um: %2b, ur: %2b, dl: %2b, dm: %2b, dr: %2b"
, $time , ldngUp , hdUl , hdUm , hdUr , hdDl , hdDm , hdDr);
$display( " cl: %1b, cm: %1b, cr: %1b", chsLf, chsMd, chsRg);
$display( "ld: %1b", d_loadingDown);
end
endmodule
Code:
Parsing design file 'design.sv'
Parsing design file 'testbench.sv'
Top Level Modules:
t23_sPivots_Bug
TimeScale is 1 ns / 1 ns
Starting vcs inline pass...
1 module and 0 UDP read.
recompiling module t23_sPivots_Bug
rm -f _cuarc*.so _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
if [ -x ../simv ]; then chmod a-x ../simv; fi
g++ -o ../simv -rdynamic -Wl,-rpath='$ORIGIN'/simv.daidir -Wl,-rpath=./simv.daidir -Wl,-rpath=/apps/vcsmx/vcs/U-2023.03-SP2/linux64/lib -L/apps/vcsmx/vcs/U-2023.03-SP2/linux64/lib -Wl,-rpath-link=./ objs/amcQw_d.o _332_archive_1.so SIM_l.o rmapats_mop.o rmapats.o rmar.o rmar_nd.o rmar_llvm_0_1.o rmar_llvm_0_0.o -lvirsim -lerrorinf -lsnpsmalloc -lvfs -lvcsnew -lsimprofile -luclinative /apps/vcsmx/vcs/U-2023.03-SP2/linux64/lib/vcs_tls.o -Wl,-whole-archive -lvcsucli -Wl,-no-whole-archive /apps/vcsmx/vcs/U-2023.03-SP2/linux64/lib/vcs_save_restore_new.o -ldl -lc -lm -lpthread -ldl
../simv up to date
CPU time: .443 seconds to compile + .375 seconds to elab + .391 seconds to link
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 10 14:35 2025
t: 0, lu: 0, ul: 00, um: 10, ur: 10, dl: 00, dm: 00, dr: 00
cl: 0, cm: x, cr: x
ld: x
$finish called from file "testbench.sv", line 26.
$finish at simulation time 3
V C S S i m u l a t i o n R e p o r t
Time: 3 ns
CPU Time: 0.460 seconds; Data structure size: 0.0Mb
Mon Feb 10 14:35:34 2025
Done