What is VIH(AC)? Can we get it through simulation?

[phoebex]

vih(ac)

Hello, All

As stated in the JEDEC,
VIH(dc) is dc input logic high, VIH(AC) is ac input logic high.
or they can be described like this:
"Once the receiver input has crossed the VIH(AC), the receiver will change to logic 1. The logic 1 will then be maintained as long as the input stays beyond VIH(dc)."

VIH(dc) can be simulated by DC sweep. My question is how to simulate VIH(AC). Anyone can help on this?

Thanks!

 

[supreet_95]

what is vih

Hi ,
Vih is basically a dc phenomenon, but due to hysterysis effects present in some circuits, it will differ from Vih(dc) depending on input signal transient behaviour. U can give a PWL waveform at input with relevant rise time (1us or 1ms) and see the cross over of input output which will give u Vih. The higher rise time like 1ms will give almost the Vih(dc). Due to hysteresis the Vih will be rise time dependent slightly. Hope i was able to help.
Supreet

 

[phoebex]

what is vih?

I agree with you on the meturement part, but I have qustion on the "hysteresis".
Is it necessary to be hysteresis input if the spec requires AC threshold voltage?

I have tried a test case with a CMOS INV and Schmmit trigger INV inside.
Under one PVT condition:
DC sweep result: VIH(inv)=0.9V; VIH(schm)=1.13V;
triangle PWL input /\ with 1ms gives the same result as DC sweep since the rise time is long enough to be regarded as DC.

Then I tried some extreme cases
Setup 1:
triangle PWL input /\ with 2ns rise time & voltage swing is from 0 to am_va; sweep am_va from 0.9 to 1.3 with 0.05V step
Result: To reach Voh (i.e. 1.5V),
am_va(inv)=1.05; am_va(schm)=1.25
I assume the above two values are the VIH(ac) of each inv.

Setup 2:
The difference from setup 1:
It is like a square wave with 1ns rise time + 1ns pulse width + 1ns fall time.
Result:
am_va(inv)=0.95; am_va(schm)=1.2
It is very close to the DC result (simulation step is 0.05V)

So, now I am confused again about the VIH(ac) spec.
When designing the input buffer, how to make sure the design can meet the VIH(ac) spec?

Sorry about the messy description above.
Thanks in advance for helping to clarify it.

 

[forrestlee]

hi, i am always confused by the "vih(ac)" and "vih(dc)".
so "Once the receiver input has crossed the VIH(AC), the receiver will change to logic 1. The logic 1 will then be maintained as long as the input stays beyond VIH(dc)."

so where are the definition from?

my email is
masterlwl@hotmail.com

thank you

 

[dick_freebird]

I've never seen the VIH(AC) spec but it's been decades
since I designed logic piece-parts. Still the hysteresis
point is a good one, many input buffers have at least
some designed hysteresis and you have to go over that
hump.

If you do a transient simulation with a slow ramp L-H and
sample the input signal at the output switchpoint, that
is going to be your VIH(AC).