what is useful skew ?

what is useful skew ?

Useful skew-If clock is skewed intentionally to resolve violations, it is called useful skew.

For example there is setup violation in the design, Then we add some skew along the clock path in order to eliminate the setup violation. I hope you know the timing violations setup and hold violation basics. Correct me if i am wrong

Thanks,
Alam

For me, usefull skew is the skew between flops which have timing path in common.
I means, the (normal) skew, is for all flops independently if these flops have no common paths.

Then we add some skew along the clock path in order to eliminate the setup violation

Click to expand...

How to add skew along the clock path? I think you can allow tool to use 'useful skew' in fixing any setup/hold violation during postCTS.

Does the tool just redo the clock tree routing?

For ideal clocking situations where every part of the chip is clocking synchronously one would need to achieve perfect clocks. This is where high performance CPU designs requires close to zero skew as possible.
However, lower-geometry physics means that ideal clocking situation is less achievable and could be "useful". This enables timing violations to be fixable through other means than just logic optimization. With useful skew, you can fix timing violations by actually *adjusting* clock arrival times at the registers.

Useful skew is leveraged by Place and Route (like Synopsys ICC and Cadence EDI) tools at the backend. Its mostly a Physical activity since, timing violations can be calculated at that level and useful skew can be adjusted by the use of clock buffers, re-adjusting the routes and re-placement of the cells and macros . . .

Cheers!
Mike

Okay sample this :-
You have three registers A B C each getting the same clock A.
Now, the latency of clockA in A is 1 (slack 12 say) clockA in B 12 (slack -12) So clock B is setup violated. There are many ways of fixing setup violation like adding buffers to speed up the data path etc... but let us assume that we cannot use any of this and the only possible way to get this done is tweak the clock path (quite dangerous). Since Setup slack = required time (clock) - arrival time (data) if i reduce the required time my slack violation will cease. Now, i add delay buffers in clock path after clock A in A (not before) so that only the clock A for B is delayed.
Interesting to note here is that delay in clock path for B will also delay data path for the flop to which the output of flop B goes (assume C) If this C has setup margin such that B can add that delay only then can you use the skew. This is called useful skew which is used to fix violations by taking slack from some and giving it to the other,

Ro9ty