What is typically used for SoC design flow ?

[incognito]

SoC Design Flow ?

What is typically employed ( softwares, chips ) for a SoC design flow.

Regards

 

[Jackal]

@lter@ provide "SOPC Builder" software.
Chips for example Triscend,Altera's Excalibur family and many others.

 

[Laplace]

SoC flow

is explained very well at *IBM*'s web site. @lter@'s is not very proper for SoC.

Regards,
Laplace

 

[cmoscircuit]

CA(chip articture)/floorplan------>dc/block level synthsis------>Apollo/first placement------>pc/phsisical optimize------->Apollo or Saturn/post place opt------->Apollo/CTS----->PC/post place opt------->Apollo/route---->DRCLVS
you can use plantpl also.I think itis so hard to control the clock skew.it may 0.5ns sometimes.

The SOC mthodology isnot mature

 

[cmoscircuit]

CA(chip articture)/floorplan------>dc/block level synthsis------>Apollo/first placement------>pc/phsisical optimize------->Apollo or Saturn/post place opt------->Apollo/CTS----->PC/post place opt------->Apollo/route---->DRCLVS
you can use plantpl also.I think itis so hard to control the clock skew.it may 0.5ns sometimes.

The SOC mthodology isnot mature

 

[SeanC]

Hi,
Have you concerned about RF/Analog core in your SOC design flow if you are doing a wireless system? Which EDA can do it well?

Thanks

SeanC

 

[okguy]

In mixed signal, the most difficult is the interface.
It requiers many reviews.
At the end, many solution exist to check, but none is perfect :
- verilog-A
- Hsim or equiv.
- Smash

For layout ... as usual ... Cadence.

OkGuy?