What is timeborrowing related to Static timing anaylsis?

[davyzhu]

timing borrow

Hi all,

I was asked in a interview, but I am not familar with Primetime.

"What is timeborrowing related to Static timing anaylsis in Primetime?"

Any suggestions will be appreciated!
Best regards,
Davy

 

[eda_wiz]

latch static timing

if u have a latch in your design and you are not using one full clock cycle for the latch... you could use the unused clock period for next or previous combinationl logic.. this idea is called time borrowing

**broken link removed**

refer this page too

 

[tarkyss]

timing given borrow

borrow time from neighborhood stage
for example, the delay between two fllip-flops may be too long, but the delay between next two flip-flops is very short, so time can be borrowed from the next stage

 

[luancao]

timing borrowing

It's a synthesis function instead of timing analysis.

 

[davyzhu]

timing-borrow

Hi all,

What's the difference between "Timing borrow" and "Retiming"?

Best regards,
Davy

 

[yeewang]

timing borrow

timing borrow, we refer to use latch to borrow time, which is typically half a cycle.

retiming, is to move register forward or backward through the combinatorial logic to balance the timing paths on every stage in the nearby register chain.

 

[ee_joe]

what is timing borrowing

timing borrow, we refer to use latch to borrow time, which is typically half a cycle.

retiming, is to move register forward or backward through the combinatorial logic to balance the timing paths on every stage in the nearby register chain.

how to use latch to borrow time?

thanks & best regards

 

[xysafety]

timing borrow in sta

As i know, in the physical implementation such as P&R can use the timeborrowing to relieve the crucial path Using the ECO

 

[anjali]

static timing balance

time borrowing means, one latch takes time of its neighbour latches, if the neighbour latches doesn't have timing violation.

Retiming means, placement of the sequential cells will be done by the tools in such a way that, they doesn't lead any timing violations.

 

[feel_on_on]

violation latch borrowed

Timing borrow happened at Latch? so gate-level netlist u synthesis include Latch? Then ..P&R tools can borrow timing ?

 

[incisive]

latch static timing analysis

**broken link removed**

 

[rascal1125]

half latch to flop timing paths

Generally, 'timing borrowing' is to use latch's behavior to make slack of previous stage or next stage met according on max. borrowing or balanced borrowing.

Other STA tool also provide 'pass-through' mode for timing analysis in latch designs, such as Incentia's TimeCraft.

Regards;

 

[isispanda]

pdf latch based static timing analysis

Hi
Can anyone help me understand "what is negative time borrowing "
thanks
Isis