what is the wrong with this code

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use STD.TEXTIO.all;
use IEEE.STD_LOGIC_TEXTIO.all;
 
ENTITY read_write_text_file_dhl IS
    PORT(   Clock : IN STD_LOGIC);
END read_write_text_file_dhl;
 
 
architecture Behavioral of read_write_text_file_dhl is
 
    file read_file : text;
    file write_file : text;
    constant filename_r : string :="D:\1.txt";
    constant filename_w : string :="D:\2.txt";
    signal dataout: std_logic_vector(3 downto 0);
 
begin
 
FILE_READ : process (Clock)
    variable line_out : line;
    variable fstatus:File_open_status;
    variable data: std_logic_vector(3 downto 0);
    variable xx: std_logic := '0';
 
begin
 
    if (xx = '0') then                                                  --------------------------
        file_open(fstatus, read_file, filename_r, read_mode);   -- the file should be --
    end if;                                                                     -- opened one time only --
                                                                                --------------------------
    if rising_edge(Clock) then
        if (not endfile(read_file)) then
            readline(read_file,line_out);
            read(line_out, data);
            dataout <= data;
        end if;
    end if;
    xx := '1';
end process FILE_READ;
 
-------------------------------------------------
 
FILE_WRITE : process (Clock)
    
    variable line_out : line;
    variable fstatus:File_open_status;
    variable zz: std_logic := '0';
 
 
begin
 
    if (zz = '0') then
    file_open(fstatus,write_file,filename_w,write_mode);
    end if;
--------------------------------
    if rising_edge(Clock) then
            write(line_out, dataout);
            writeline(write_file, line_out);
    end if;
    zz := '1';
 
end process FILE_WRITE;
 
--------------------------------------------------
 
end Behavioral;