1. Splitting a plane is done to permit more than one voltage or ground return region to be used on a single layer. For example, you could have 5VDC, 3.3VDC, 12VDC, and 1.2VDC all on the same layer by splitting the plane into isolated regions of copper for each voltage. Likewise, you could have an analog ground region on the same plane layer as a digital ground region by splitting the copper into isolated regions.
2. Each EDA package has its own way of defining the net assigned to a split plane region. It depends on what software you are running.
3. The "rules" for split planes really are design considerations for the signal layers that are adjacent to the planes. For example, you want to avoid routing a signal trace over the void between splits - it creates a discontinuity in the trace impedance that has to be compensated for with bypass capacitors. You want to avoid running a signal trace over a split that is unrelated to the signal (for example, you wouldn't want to run an analog signal trace over a region of digital ground returns, or a sensitive signal over a split used to supply power to relays).
4. You can have splits on as many plane layers as you want. Just keep in mind the signal sensitivities noted above. Also remember that the splits on different plane layers that belong to a single net have to be connected together such that you have a sensible current flow from source to sink. All of that copper couples to nearby board structures capacitively - you need to be sure that you control that coupling to protect signal integrity and prevent EMI.