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when u design..u first make a schematic entry..u adjust transistor sizes so that the o/p is ok...then u make the layout according to the schematic..then u extract the schematic to a spice file ..u also have then to extract the layout to a spice file...then LVS DOES a comparision of them to check if both are matching...actually its a tool for verifying if you layout matches your schematic...thats all...
when u design..u first make a schematic entry..u adjust transistor sizes so that the o/p is ok...then u make the layout according to the schematic..then u extract the schematic to a spice file ..u also have then to extract the layout to a spice file...then LVS DOES a comparision of them to check if both are matching...actually its a tool for verifying if you layout matches your schematic...thats all...
in s-edit u have the export button..i.e u can export this to a file names xyz.sp(sp for spice)(or some other standard formats also..but presently we need this only)...then it will generate the spice file for you...make yourself sure about the location of the spice file while extracting.In L-edit..u click the tspice icon ..u can get the netlist and u can see this file as the tspice window opens up.....
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