genvar 1;
generate
for (i = 0; i < num_chan; i = i+1)
begin : loop_label
a1 : assert property(p_req_gets_resp(i));
if (i < 5)
c1 : cover property (p_max_latency(i));
end
endgenerate
My Doubt is --> What is the use of generate statement here ??? How does it differ from the for loop???
Hi,
The Generate Statement in Verilog differs from the for loop, that it adds a specific parts of verilog code to the module depending on the conditions, which helps that the code in a module ---> Instance functionality , can be variable according to the parameter passed to the module for example.