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i dont think it is quantifiable... because ESD occurs once the voltage strength acquires a particular value i.e__kV/cm.... so you cant measure the time for which a particular voltage strength doesn't affect the IC pin.....
actually ESD standard says that esd will be applied and tested on the user accessible points
when u r refering to the ic pin, i cannot be a valid as the whole ic will be seeing the esd if the ic is user accessible or any charge cna pass to its pins through routing from the user accessible points, in this case the ic data sheet says how much the ic can with stand the esd
Each Pin in any IC package should be able to handle upto 2KV. This is according to Maching model. Since, parts should be maching placeable without distruction.
at HBM 2KV a current up to 1.5A will go through the PINs for several nano seconds. your ESD circuits must dissipate the so high ESD power in such a shot time. If the heat generate by the ESD power is so concentrated in small size, you ESD circuit may fail. Good Luck.
Your question should be sth like
(1) What is the ESD stress time for different ESD standard?
(2) What is the time a PMOS or NMOS can withstand some voltage high enough like ESD?
If (1), you can refer to ESD standard ranging from severa tens of ns in HBM or several ns in MM or CDM
If (2), you can refer to process foundry for device tolerance, but usually, not more than several us range if a high voltage is supplied to device. But that high voltage is only limited to something VDDx2 voltage, instead of ESD voltage,
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