To a RS latch.
I have the same puzzle. By the way, what's difference between block assignment and non-block assignment in combin logic? Thank you very much~
The code does not specify an assigned value for the condition (I1 == 1 && I2 == 1), so the previous value must be preserved, in other words a latch is generated. The value is not undefined.Will not the synthesis tool take the other conditions for I1 and I2 as X because the else condition is not defined here? How do the synthesis tool generate a latch because other conditions for I1 and I2 are not defined.
The value is not undefined.
The code does not specify an assigned value for the condition (I1 == 1 && I2 == 1), so the previous value must be preserved, in other words a latch is generated.
The always@(*) will only execute when any of the input variables change. Since your inputs are all constants this rtl will never execute and synthesis should not produce anything
Hi Sun_ray, would you please give me a link for this document? Thank you~
always (*)
if (en) o <= i;my_signal1 <= !I1;
my_signal2 <= I1;Do you understand that the below behavioral statement describes a latch (hold the previous state while en == 0)?
Code:always (*) if (en) o <= i;
What do you want to mean by stating that the code in post #9 isn't? What do you mean by isn't? Do you want to mean that the code in post no. # 9 is not a latch.The code in post #9 isn't but a long winded way to write
For input conditions that don't specify an assigned value, the previous value will be preserved. In other words a latch is generated. Your Verilog textbooks should tell about this.But the question here also remains how the above rtl specify to preserve the value when en == 0, because the above rtl does not specify anything when en == 0.
Indeed it's no latch. I already told what it is.Do you want to mean that the code in post no. # 9 is not a latch.
6.2 Procedural assignments
The primary discussion of procedural assignments is in 9.2. However, a description of the basic ideas in this clause highlights the differences between continuous assignments and procedural assignments.
As stated in 6.1, continuous assignments drive nets in a manner similar to the way gates drive nets. The expression on the right-hand side can be thought of as a combinatorial circuit that drives the net continuously. In contrast, procedural assignments put values in variables. The assignment does not have duration; instead, the variable holds the value of the assignment until the next procedural assignment to that variable.
Indeed it's no latch. I already told what it is.
Yes, a complete conditional branch with complete output assignments in a level sensitive always block models combinational logic, in this case a simpler buffer respectively inverter.Do you want to mean that mysignal1 is the output of an inverter with I1 as the input and my_signal is a buffer with I1 as the input?
I personally prefer the Verilog LRM IEEE 1364 (or System Verilog IEEE 1800, which includes basic Verilog as a subset) and the standard for synthesizable Verilog IEEE 1364.1 as reference. But as said, the topics are also presented in most text books.
I don't agree, basically it's all in the LRM. Some RTL specific points are clarified in 1364.1 IEEE Standard for Verilog® Register Transfer Level Synthesis.
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