What is the syntex of synchronous reset in VHDL?

[bigyellow]

should it be

if clk'event and clk = '1' then 
   if reset = '0'  then 
        ------
   else 
       if ........then

       elsif.......then 
          -------
       else
           --------
       end if; 
   end if;
end if;

or

if clk'event and clk = '1' then 
   if reset = '0'  then 
        ------
   elsif .........then
       ------------
   elsif ...........then
      ---------
   else
       ------------
   end if;
end if;

 

[jitendra]

hi,
first code is more appropriate. Writing elsif in reset condition is not a proper practice.

e.g. Code for D FF with Synch reset is

signal D, Q, clk, reset : bit ;
...
process (clk)
begin
    if (clk’event and clk = ’1’) then
        if reset = ’1’ then
            D <= ’0’ ;
        else
            -- you can write if or case statement within this else part
            Q <= D ;
        end if ;
    end if ;
end process ;

Regards,
JItendra

 

[akrlot]

hi,
first code is more appropriate. Writing elsif in reset condition is not a proper practice.

e.g. Code for D FF with Synch reset is

signal D, Q, clk, reset : bit ;
...
process (clk)
begin
    if (clk’event and clk = ’1’) then
        if reset = ’1’ then
            D <= ’0’ ;
        else
            -- you can write if or case statement within this else part
            Q <= D ;
        end if ;
    end if ;
end process ;

Regards,
JItendra

The process of DFF depends also on signal reset so you need to add it to its sensibility list.

process (clk,reset)
begin
--code here
end process;

 

[jitendra]

Hi,
In case of synchronous reset, reset signal is not required in sensitivity list as reset will be sampled on active clock edge only. Where as in asynchronous reset it is necessary to include reset signal in sensitivity list because it is supposed to function independent of clock signal.

Regards,
Jitendra

The process of DFF depends also on signal reset so you need to add it to its sensibility list.

process (clk,reset)
begin
--code here
end process;

 

[nittinsharma80]

yes,
for simulation if its synchronous then it should be activated on clk signal only
that why only clk in the sensitivity list.
how ever because of this there can be a simulation mismatch b/n synthesis and symulation of the same.
comment invited....

 

[amraldo]

The first form is more appropriate.
There is no need for reset in the process sensitivity list in case of synchronous rest.
In case of a synchronous reset, the eset must be in the sensitivity list. But take care that only one signal of clock or reset can be edge sensitive. There is no process sensitive for 2 clocks.
for example:
process(reset, clock)
begin
if reset = X then
ur code
elsif rising_edge(clock)
ur code
end if
end process

 

[rprince006]

the correct coding style for an FSM with async reset in VHDL:

process (clk, reset_n) -- for FSM
begin
if reset_n = '0' then
state <= IDLE;
elsif clk'event and clk = '1' then
state <= next_state;
endif
end process;

process (clk, reset_n) -- for registerd logic
begin
if reset_n = '0' then
signals <= '0'
elsif clk'event and clk = '1' then
if ... then
elsif .... then
else
endif;
endif;
end process;


Note: the process has to react first to reset_n signal before it reacts to
the clk event for an async logic.

Cheers,
Rprince006,