what is the significance of Seed value for RTL simulation ?

what is the significance of Seed value for RTL simulation ? I have run testcase with one seed value and it's passing. Then I ran the same testcase with othe seed value and it's failing..!!..What it means ?..IS it bug in dut ?
How can we be sure that we have covers all possible values of seeds during verification ?

Take a look at https://en.wikipedia.org/wiki/Random_seed

If the testcase (and/or other parts of your testbench) run against your DUT is random, then it can generate a different set of stimuli to the DUT on a different seed. We can't definitely say it is a DUT bug, as it can happen to be a testcase bug. So, until you haven't debugged the problem it is hard to say.

The answer to your next question is quite involved, and to some extend it is an area of research. There is no way to cover all possible values of seeds (i.e. a seed is a 32-bit value), but a general practice is to utilize code and functional coverage to monitor/measure how well your random testcases are covering the DUT.

seed value matters only when you have defined some variable as rand [specific to system verilog] or field getting its value from $urandom types of functions.

the simulaters assign value to such variables on the solving the random value generator [which is internal function of simulator]. Thus when you run a testcase wtih different seed it actually assign different values to your field. like
bit [4:0] addr -> will always have value of '0' what ever may be the seed
and for rand bit [4:0] addr -> will have different value as per seed, and it will always give same value with same seed.

so now in your case with different seed, different value will be feeded to RTL and may be RTL has bug with that particular stimulus.


you can run with n number of seed values. We never say we have covered this much of seeds, its coverage that defines the requirement of running the same testcase with different different seeds

Hope this description help you

Best of luck