One more things is, may i know how you come out with that percentage with the RC? For my simulation, the 1RC = 300 us. But what i see, 40 us already settle and quite stable or equivalent to 40/300 = 13 % stabilization. It is make sense?
No, it does't make sense ...
Values (%) were taken from RC - time constant graph:
h**p://www.interfacebus.com/Design_RC_Rising_Time_Constant_Graph.html
settling time -is he time taken to reach a value(+ or -2 % of final value in general)
so here it is the time taken to reach 98% which is nothing but 4RC .
Like the earlier posts, you should be clear about the value till which the signal settles. Normal standards would be anywhere between 1 - 5% of the input value. One crucial thing you should note is that, since it is a first order circuit, the circuit has not other option but to settle. You will never notice any oscillations.
Like the earlier posts, you should be clear about the value till which the signal settles. Normal standards would be anywhere between 1 - 5% of the input value. One crucial thing you should note is that, since it is a first order circuit, the circuit has not other option but to settle. You will never notice any oscillations.
ya. I understand about that. My expexted value is ard 1.2v when settle. It take only 40 us to reach this value. The signal will start with big osilation at the starting point and reduce to almost flat at 1.2v in 40 us. But my RC is 400 us. That mean less than 1RC, the signal almost 100 % settle. It is not acording to the formula
given. Am i right?
one more thing is, the signal that i take is from a close-loop feedback system.
If you can post the schematics, may be we can look into it. It is not possible to settle so fast with a first order situation. May be the higher order blocks is causing the output to rise faster. Is there an active block in the closed loop system, which is forcing the output to rise faster than a passive circuit?
If you can post the schematics, may be we can look into it. It is not possible to settle so fast with a first order situation. May be the higher order blocks is causing the output to rise faster. Is there an active block in the closed loop system, which is forcing the output to rise faster than a passive circuit?
i think the formula given, is for the a capacitor to charge or discharge up to certain value. But my question is about the settilng time. The signal will have some ringing, after that settle down, is it both the same? If yes, any formula to link it?
The concept of settling comes only when higher order transfer functions are there. In case you have used an OPamp, you get the settling considering the GBW of the opamp,which changes in frequency. Like I have said earlier, you cannot get ringing with First order. I usually calculate things manually transforming the s-domain equations to time domain.
i do believe the 5RC is for RC constant time that is used to determine the capacitor charging and discharging time.
for the settling time, it depends on the phase margin and dampling ratio of ur closed loop system. ideally 0.7 dampling ration and 60' phase margin will form a undamp output in trans response.